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Fix decoder issues (stop of i2c, break of dmx512)

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DreamSourceLab
2020-04-02 10:09:51 +08:00
parent beb06ca1be
commit c6bdd0e5ed
3 changed files with 24 additions and 8 deletions
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12
libsigrokdecode4DSL/decoders/0-i2c/pd.py
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@@ -249,6 +249,12 @@ class Decoder(srd.Decoder):
elif (self.matched & (0b1 << 2)):
self.handle_stop()
elif self.state == 'FIND ACK':
# Wait for a data/ack bit: SCL = rising.
(scl, sda) = self.wait({0: 'r'})
self.get_ack(scl, sda)
# Wait for any of the following conditions (or combinations):
# a) a data/ack bit: SCL = rising.
# b) STOP condition (P): SCL = high, SDA = rising
(scl, sda) = self.wait([{0: 'r'}, {0: 'h', 1: 'r'}])
if (self.matched & (0b1 << 0)):
self.get_ack(scl, sda)
elif (self.matched & (0b1 << 1)):
self.handle_stop()

12
libsigrokdecode4DSL/decoders/1-i2c/pd.py
View File

@@ -285,6 +285,12 @@ class Decoder(srd.Decoder):
elif (self.matched & (0b1 << 2)):
self.handle_stop()
elif self.state == 'FIND ACK':
# Wait for a data/ack bit: SCL = rising.
(scl, sda) = self.wait({0: 'r'})
self.get_ack(scl, sda)
# Wait for any of the following conditions (or combinations):
# a) a data/ack bit: SCL = rising.
# b) STOP condition (P): SCL = high, SDA = rising
(scl, sda) = self.wait([{0: 'r'}, {0: 'h', 1: 'r'}])
if (self.matched & (0b1 << 0)):
self.get_ack(scl, sda)
elif (self.matched & (0b1 << 1)):
self.handle_stop()

8
libsigrokdecode4DSL/decoders/dmx512/pd.py
View File

@@ -83,12 +83,13 @@ class Decoder(srd.Decoder):
inv = self.options['invert'] == 'yes'
(dmx,) = self.wait({0: 'h' if inv else 'l'})
self.run_start = self.samplenum
while True:
# Seek for an interval with no state change with a length between
# 88 and 1000000 us (BREAK).
if self.state == 'FIND BREAK':
(dmx,) = self.wait({0: 'h' if inv else 'l'})
self.run_start = self.samplenum
(dmx,) = self.wait({0: 'f' if inv else 'r'})
runlen = (self.samplenum - self.run_start) * self.sample_usec
if runlen > 88 and runlen < 1000000:
@@ -98,6 +99,9 @@ class Decoder(srd.Decoder):
elif runlen >= 1000000:
# Error condition.
self.putr([10, ['Invalid break length']])
else:
(dmx,) = self.wait({0: 'h' if inv else 'l'})
self.run_start = self.samplenum
# Directly following the BREAK is the MARK AFTER BREAK.
elif self.state == 'MARK MAB':
self.run_start = self.samplenum