forked from Ivasoft/DSView
add c2 decoder
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DreamSourceLab
32
libsigrokdecode4DSL/decoders/c2/__init__.py
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libsigrokdecode4DSL/decoders/c2/__init__.py
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##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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'''
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The SPI (Serial Peripheral Interface) protocol decoder supports synchronous
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SPI(-like) protocols with a clock line, a MISO and MOSI line for data
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transfer in two directions, and an optional CS# pin.
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Either MISO or MOSI (but not both) can be optional.
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If CS# is supplied, data is only decoded when CS# is asserted (clock
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transitions where CS# is not asserted are ignored). If CS# is not supplied,
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data is decoded on every clock transition (depending on SPI mode).
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'''
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from .pd import Decoder
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204
libsigrokdecode4DSL/decoders/c2/pd.py
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libsigrokdecode4DSL/decoders/c2/pd.py
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import sigrokdecode as srd
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'''
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'''
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class ChannelError(Exception):
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pass
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'C2'
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name = 'C2 interface'
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longname = 'Silabs C2 Interface'
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desc = 'Half-duplex, synchronous, serial bus.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = ['C2']
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tags = ['Embedded/mcu']
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channels = (
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{'id': 'c2ck', 'type': 0, 'name': 'c2ck', 'desc': 'Clock'},
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{'id': 'c2d', 'type': 0, 'name': 'c2d', 'desc': 'Data'},
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)
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optional_channels = ()
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annotations = (
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('106', 'raw-Data', 'raw data'),
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('106', 'c2-data', 'c2 data'),
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('warnings', 'Warnings'),
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)
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annotation_rows = (
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('raw-Data', 'raw data', (0,)),
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('c2-data', 'c2 data', (1,)),
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('warnings', 'Warnings', (2,)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.samplerate = None
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self.state= 'reset'
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self.bitcount = 0
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self.c2data = 0
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self.data=0
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self.c2dbits = []
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self.ss_block = -1
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self.samplenum = -1
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self.have_c2ck = self.have_c2d = None
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self.ins= None
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self.dataLen=0
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self.remainData=0
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def metadata(self, key, value):
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if key == srd.SRD_CONF_SAMPLERATE:
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self.samplerate = value
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def decode(self):
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if not self.has_channel(0):
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raise ChannelError('CLK pin required.')
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self.have_c2d = self.has_channel(1)
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if not self.have_c2d:
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raise ChannelError('C2D pins required.')
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tf=0
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tr=0
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while True:
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(c2ck,c2d)=self.wait({0:'e'})
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if c2ck == 0: #ϽµÑØ
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tf=self.samplenum
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if self.state == 'dataRead':
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if self.bitcount ==0:
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ss=tr
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self.c2data=0
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self.c2data |= c2d <<self.bitcount
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self.bitcount += 1
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if self.bitcount >= 8:
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self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]])
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self.bitcount=0
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self.data|=self.c2data<<((self.dataLen-self.remainData)*8)
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self.remainData -= 1
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if self.remainData ==0:
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self.state = 'end'
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elif self.state == 'addressRead':
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if self.bitcount ==0:
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ss=tr
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self.c2data=0
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self.c2data |= c2d <<self.bitcount
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self.bitcount += 1
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if self.bitcount >= 8:
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self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]])
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self.state = 'end'
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elif self.state == 'readWait':
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if self.bitcount ==0:
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ss=tf
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self.bitcount +=1
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if c2d == 1:
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self.put(ss, tf, self.out_ann, [0, ['Wait','W']])
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self.bitcount=0
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self.state = 'dataRead'
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elif self.state == 'writeWait':
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if self.bitcount ==0:
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ss=tr
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self.bitcount += 1
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if c2d == 1:
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self.put(ss, tf, self.out_ann, [0, ['Wait','W']])
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self.state = 'end'
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else: #ÉÏÉýÑØ
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tr=self.samplenum
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interval=(tr-tf)*1000*1000/self.samplerate #us
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if interval>20:
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self.put(tf, tr, self.out_ann, [0, [ 'Reset','R']])
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self.state='start'
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elif self.state == 'start':
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self.put(tf, tr, self.out_ann, [0, [ 'Start','S']])
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self.state='ins'
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self.bitcount=0
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self.ins=0
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self.data=0
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self.dataLen=0
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ss1=tf
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elif self.state == 'ins':
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if self.bitcount ==0:
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ss=tr
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self.c2data=0
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self.ins |= c2d <<self.bitcount
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self.bitcount += 1
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if self.bitcount >= 2:
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(c2ck,c2d)=self.wait({0:'f'})
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if self.ins == 0 :
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self.state = 'dataReadLen'
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elif self.ins == 2:
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self.state = 'addressRead'
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elif self.ins == 1:
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self.state = 'dataWriteLen'
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else:
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self.state = 'addressWrite'
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self.put(ss, self.samplenum, self.out_ann, [0, [ '%1d'%self.ins]])
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self.bitcount=0
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elif self.state == 'addressWrite':
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if self.bitcount ==0:
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ss=tr
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self.c2data=0
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self.c2data |= c2d <<self.bitcount
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self.bitcount += 1
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if self.bitcount >= 8:
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(c2ck,c2d)=self.wait({0:'f'})
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tf=self.samplenum
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self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]])
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self.bitcount=0
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self.state = 'end'
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elif self.state == 'dataReadLen':
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if self.bitcount ==0:
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ss=tr
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self.c2data=0
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self.c2data |= c2d <<self.bitcount
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self.bitcount += 1
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if self.bitcount >= 2:
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self.dataLen=self.c2data+1
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self.remainData=self.dataLen
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#(c2ck,c2d)=self.wait({0:'f'})
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self.put(ss, self.samplenum, self.out_ann, [0, [ '%01d'%self.c2data]])
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self.state='readWait'
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self.bitcount=0
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elif self.state == 'dataWriteLen':
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if self.bitcount ==0:
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ss=tr
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self.c2data=0
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self.c2data |= c2d <<self.bitcount
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self.bitcount += 1
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if self.bitcount >= 2:
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self.dataLen=self.c2data+1
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self.remainData=self.dataLen
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(c2ck,c2d)=self.wait({0:'f'})
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self.put(ss, self.samplenum, self.out_ann, [0, ['%01d'%self.c2data]])
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self.state='dataWrite'
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self.bitcount=0
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self.c2data=0
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elif self.state == 'dataWrite':
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if self.bitcount ==0:
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ss=tr
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self.c2data=0
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self.c2data |= c2d <<self.bitcount
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self.bitcount += 1
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if self.bitcount >= 8:
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self.put(ss, tr, self.out_ann, [0, ['%02X' % self.c2data]])
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self.bitcount=0
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self.data|=self.c2data<<((self.dataLen-self.remainData)*8)
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self.remainData -= 1
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if self.remainData ==0:
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self.state='writeWait'
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elif self.state == 'end':
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self.state='start'
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self.put(tf, tr, self.out_ann, [0, [ 'End','E']])
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if self.ins == 0:
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self.put(ss1, tr, self.out_ann, [1, [ 'ReadData(%01d)=0x%02X'%(self.dataLen,self.data)]])
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elif self.ins == 1:
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self.put(ss1, tr, self.out_ann, [1, [ 'WriteData(0x%02X,%01d)'%(self.data,self.dataLen)]])
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elif self.ins == 2:
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self.put(ss1, tr, self.out_ann, [1, [ 'ReadAddress()=0x%02X'%self.c2data]])
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elif self.ins == 3:
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self.put(ss1, tr, self.out_ann, [1, [ 'WriteAddress(0x%02X)'%self.c2data]])
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