From 8c5af3f36588d3d27268c145d9984036f6631297 Mon Sep 17 00:00:00 2001 From: DreamSourceLab Date: Mon, 27 Jun 2022 09:29:13 +0800 Subject: [PATCH] add c2 decoder --- libsigrokdecode4DSL/decoders/c2/__init__.py | 32 +++ libsigrokdecode4DSL/decoders/c2/pd.py | 204 ++++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 libsigrokdecode4DSL/decoders/c2/__init__.py create mode 100644 libsigrokdecode4DSL/decoders/c2/pd.py diff --git a/libsigrokdecode4DSL/decoders/c2/__init__.py b/libsigrokdecode4DSL/decoders/c2/__init__.py new file mode 100644 index 00000000..dc5cbc05 --- /dev/null +++ b/libsigrokdecode4DSL/decoders/c2/__init__.py @@ -0,0 +1,32 @@ +## +## This file is part of the libsigrokdecode project. +## +## Copyright (C) 2012 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +''' +The SPI (Serial Peripheral Interface) protocol decoder supports synchronous +SPI(-like) protocols with a clock line, a MISO and MOSI line for data +transfer in two directions, and an optional CS# pin. + +Either MISO or MOSI (but not both) can be optional. + +If CS# is supplied, data is only decoded when CS# is asserted (clock +transitions where CS# is not asserted are ignored). If CS# is not supplied, +data is decoded on every clock transition (depending on SPI mode). +''' + +from .pd import Decoder diff --git a/libsigrokdecode4DSL/decoders/c2/pd.py b/libsigrokdecode4DSL/decoders/c2/pd.py new file mode 100644 index 00000000..8cdc8ec5 --- /dev/null +++ b/libsigrokdecode4DSL/decoders/c2/pd.py @@ -0,0 +1,204 @@ +import sigrokdecode as srd + +''' +''' + +class ChannelError(Exception): + pass + +class Decoder(srd.Decoder): + api_version = 3 + id = 'C2' + name = 'C2 interface' + longname = 'Silabs C2 Interface' + desc = 'Half-duplex, synchronous, serial bus.' + license = 'gplv2+' + inputs = ['logic'] + outputs = ['C2'] + tags = ['Embedded/mcu'] + channels = ( + {'id': 'c2ck', 'type': 0, 'name': 'c2ck', 'desc': 'Clock'}, + {'id': 'c2d', 'type': 0, 'name': 'c2d', 'desc': 'Data'}, + ) + optional_channels = () + annotations = ( + ('106', 'raw-Data', 'raw data'), + ('106', 'c2-data', 'c2 data'), + ('warnings', 'Warnings'), + ) + annotation_rows = ( + ('raw-Data', 'raw data', (0,)), + ('c2-data', 'c2 data', (1,)), + ('warnings', 'Warnings', (2,)), + ) + + def __init__(self): + self.reset() + + def reset(self): + self.samplerate = None + self.state= 'reset' + self.bitcount = 0 + self.c2data = 0 + self.data=0 + self.c2dbits = [] + self.ss_block = -1 + self.samplenum = -1 + self.have_c2ck = self.have_c2d = None + self.ins= None + self.dataLen=0 + self.remainData=0 + + def start(self): + self.out_ann = self.register(srd.OUTPUT_ANN) + + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value + + def decode(self): + if not self.has_channel(0): + raise ChannelError('CLK pin required.') + self.have_c2d = self.has_channel(1) + if not self.have_c2d: + raise ChannelError('C2D pins required.') + tf=0 + tr=0 + while True: + (c2ck,c2d)=self.wait({0:'e'}) + if c2ck == 0: #ϽµÑØ + tf=self.samplenum + if self.state == 'dataRead': + if self.bitcount ==0: + ss=tr + self.c2data=0 + self.c2data |= c2d <= 8: + self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]]) + self.bitcount=0 + self.data|=self.c2data<<((self.dataLen-self.remainData)*8) + self.remainData -= 1 + if self.remainData ==0: + self.state = 'end' + elif self.state == 'addressRead': + if self.bitcount ==0: + ss=tr + self.c2data=0 + self.c2data |= c2d <= 8: + self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]]) + self.state = 'end' + elif self.state == 'readWait': + if self.bitcount ==0: + ss=tf + self.bitcount +=1 + if c2d == 1: + self.put(ss, tf, self.out_ann, [0, ['Wait','W']]) + self.bitcount=0 + self.state = 'dataRead' + elif self.state == 'writeWait': + if self.bitcount ==0: + ss=tr + self.bitcount += 1 + if c2d == 1: + self.put(ss, tf, self.out_ann, [0, ['Wait','W']]) + self.state = 'end' + + else: #ÉÏÉýÑØ + tr=self.samplenum + interval=(tr-tf)*1000*1000/self.samplerate #us + if interval>20: + self.put(tf, tr, self.out_ann, [0, [ 'Reset','R']]) + self.state='start' + elif self.state == 'start': + self.put(tf, tr, self.out_ann, [0, [ 'Start','S']]) + self.state='ins' + self.bitcount=0 + self.ins=0 + self.data=0 + self.dataLen=0 + ss1=tf + elif self.state == 'ins': + if self.bitcount ==0: + ss=tr + self.c2data=0 + self.ins |= c2d <= 2: + (c2ck,c2d)=self.wait({0:'f'}) + if self.ins == 0 : + self.state = 'dataReadLen' + elif self.ins == 2: + self.state = 'addressRead' + elif self.ins == 1: + self.state = 'dataWriteLen' + else: + self.state = 'addressWrite' + self.put(ss, self.samplenum, self.out_ann, [0, [ '%1d'%self.ins]]) + self.bitcount=0 + elif self.state == 'addressWrite': + if self.bitcount ==0: + ss=tr + self.c2data=0 + self.c2data |= c2d <= 8: + (c2ck,c2d)=self.wait({0:'f'}) + tf=self.samplenum + self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]]) + self.bitcount=0 + self.state = 'end' + elif self.state == 'dataReadLen': + if self.bitcount ==0: + ss=tr + self.c2data=0 + self.c2data |= c2d <= 2: + self.dataLen=self.c2data+1 + self.remainData=self.dataLen + #(c2ck,c2d)=self.wait({0:'f'}) + self.put(ss, self.samplenum, self.out_ann, [0, [ '%01d'%self.c2data]]) + self.state='readWait' + self.bitcount=0 + elif self.state == 'dataWriteLen': + if self.bitcount ==0: + ss=tr + self.c2data=0 + self.c2data |= c2d <= 2: + self.dataLen=self.c2data+1 + self.remainData=self.dataLen + (c2ck,c2d)=self.wait({0:'f'}) + self.put(ss, self.samplenum, self.out_ann, [0, ['%01d'%self.c2data]]) + self.state='dataWrite' + self.bitcount=0 + self.c2data=0 + elif self.state == 'dataWrite': + if self.bitcount ==0: + ss=tr + self.c2data=0 + self.c2data |= c2d <= 8: + self.put(ss, tr, self.out_ann, [0, ['%02X' % self.c2data]]) + self.bitcount=0 + self.data|=self.c2data<<((self.dataLen-self.remainData)*8) + self.remainData -= 1 + if self.remainData ==0: + self.state='writeWait' + elif self.state == 'end': + self.state='start' + self.put(tf, tr, self.out_ann, [0, [ 'End','E']]) + if self.ins == 0: + self.put(ss1, tr, self.out_ann, [1, [ 'ReadData(%01d)=0x%02X'%(self.dataLen,self.data)]]) + elif self.ins == 1: + self.put(ss1, tr, self.out_ann, [1, [ 'WriteData(0x%02X,%01d)'%(self.data,self.dataLen)]]) + elif self.ins == 2: + self.put(ss1, tr, self.out_ann, [1, [ 'ReadAddress()=0x%02X'%self.c2data]]) + elif self.ins == 3: + self.put(ss1, tr, self.out_ann, [1, [ 'WriteAddress(0x%02X)'%self.c2data]]) +