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fix: get bit from self.matched error

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This commit is contained in:
dreamsourcelabTAI
2022-03-25 14:22:04 +08:00
parent fd27873c21
commit 5b1cbbb9e9
10 changed files with 54 additions and 47 deletions
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27
libsigrokdecode4DSL/decoders/a7105/pd.py
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@@ -88,9 +88,7 @@ class Decoder(srd.Decoder):
inputs = ['spi'] inputs = ['spi']
outputs = [] outputs = []
tags = ['IC', 'Wireless/RF'] tags = ['IC', 'Wireless/RF']
options = ( options = (
{'id': 'hex_display', 'desc': 'Display payload in Hex', 'default': 'yes',
'values': ('yes', 'no')},
) )
annotations = ( annotations = (
# Sent from the host to the chip. # Sent from the host to the chip.
@@ -130,6 +128,9 @@ class Decoder(srd.Decoder):
'''Put an annotation message 'msg' at 'pos'.''' '''Put an annotation message 'msg' at 'pos'.'''
self.put(pos[0], pos[1], self.out_ann, [ann, [msg]]) self.put(pos[0], pos[1], self.out_ann, [ann, [msg]])
def put_ann(self, pos, ann, msg_arr):
self.put(pos[0], pos[1], self.out_ann, [ann, msg_arr])
def next(self): def next(self):
'''Resets the decoder after a complete command was decoded.''' '''Resets the decoder after a complete command was decoded.'''
# 'True' for the first byte after CS went low. # 'True' for the first byte after CS went low.
@@ -253,24 +254,18 @@ class Decoder(srd.Decoder):
True, all bytes are decoded as hex codes, otherwise only non True, all bytes are decoded as hex codes, otherwise only non
printable characters are escaped.''' printable characters are escaped.'''
if always_hex: def escape(b):
def escape(b):
return '{:02X}'.format(b) return '{:02X}'.format(b)
else:
def escape(b):
c = chr(b)
if not str.isprintable(c):
return '\\x{:02X}'.format(b)
return c
data = ''.join([escape(b) for b in data]) data = ''.join([escape(b) for b in data])
text = '{} = "{}"'.format(label, data.strip()) ann_arr = [label + ' = "{$}"', '@' + data]
self.putp(pos, ann, text)
self.put_ann(pos, ann, ann_arr)
def finish_command(self, pos): def finish_command(self, pos):
'''Decodes the remaining data bytes at position 'pos'.''' '''Decodes the remaining data bytes at position 'pos'.'''
always_hex = self.options['hex_display'] == 'yes' always_hex = True
if self.cmd == 'R_REGISTER': if self.cmd == 'R_REGISTER':
self.decode_register(pos, self.ann_cmd, self.decode_register(pos, self.ann_cmd,
self.dat, self.miso_bytes()) self.dat, self.miso_bytes())

4
libsigrokdecode4DSL/decoders/ade77xx/pd.py
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@@ -124,8 +124,8 @@ class Decoder(srd.Decoder):
vali = self.miso_bytes[1] vali = self.miso_bytes[1]
if write: if write:
self.putx([1, ['%s: %#x' % (rblob[0], valo)]]) self.putx([1, ['%s: {$}' % rblob[0], '@%02X' % valo]])
else: else:
self.putx([0, ['%s: %#x' % (rblob[0], vali)]]) self.putx([0, ['%s: {$}' % rblob[0], '@%02X' % valo]])
self.reset_data() self.reset_data()

2
libsigrokdecode4DSL/decoders/caliper/pd.py
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@@ -91,7 +91,7 @@ class Decoder(srd.Decoder):
# after inactivity for a user specified period. Present the # after inactivity for a user specified period. Present the
# number of unprocessed bits to the user for diagnostics. # number of unprocessed bits to the user for diagnostics.
clk, data = self.wait(wait_cond) clk, data = self.wait(wait_cond)
if timeout_ms and not self.matched[0]: if timeout_ms and not self.matched & 0b1 == 0b1:
if self.number_bits or self.flags_bits: if self.number_bits or self.flags_bits:
count = len(self.number_bits) + len(self.flags_bits) count = len(self.number_bits) + len(self.flags_bits)
self.putg(self.ss, self.samplenum, 1, [ self.putg(self.ss, self.samplenum, 1, [

6
libsigrokdecode4DSL/decoders/flexray/pd.py
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@@ -407,7 +407,7 @@ class Decoder(srd.Decoder):
# Wait until we're in the correct bit/sampling position. # Wait until we're in the correct bit/sampling position.
pos = self.get_sample_point(self.curbit) pos = self.get_sample_point(self.curbit)
(fr_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}]) (fr_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}])
if self.matched[1]: if self.matched & 0b10:
self.dom_edge_seen() self.dom_edge_seen()
if self.matched[0]: if self.matched & 0b01:
self.handle_bit(fr_rx) self.handle_bit(fr_rx)

2
libsigrokdecode4DSL/decoders/iec/pd.py
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@@ -132,7 +132,7 @@ class Decoder(srd.Decoder):
self.step = 0 self.step = 0
if self.step == 0: if self.step == 0:
# Don't use self.matched[1] here since we might come from # Don't use self.matched_[1] here since we might come from
# a step with different conds due to the code above. # a step with different conds due to the code above.
if data == 0 and clk == 1: if data == 0 and clk == 1:
# Rising edge on CLK while DATA is low: Ready to send. # Rising edge on CLK while DATA is low: Ready to send.

24
libsigrokdecode4DSL/decoders/ieee488/pd.py
View File

@@ -624,12 +624,12 @@ class Decoder(srd.Decoder):
data, clk = pins[PIN_DATA], pins[PIN_CLK] data, clk = pins[PIN_DATA], pins[PIN_CLK]
atn, = self.invert_pins([pins[PIN_ATN]]) atn, = self.invert_pins([pins[PIN_ATN]])
if self.matched[0]: if self.matched & 0b1:
# Falling edge on ATN, reset step. # Falling edge on ATN, reset step.
step = STEP_WAIT_READY_TO_SEND step = STEP_WAIT_READY_TO_SEND
if step == STEP_WAIT_READY_TO_SEND: if step == STEP_WAIT_READY_TO_SEND:
# Don't use self.matched[1] here since we might come from # Don't use self.matched_[1] here since we might come from
# a step with different conds due to the code above. # a step with different conds due to the code above.
if data == 0 and clk == 1: if data == 0 and clk == 1:
# Rising edge on CLK while DATA is low: Ready to send. # Rising edge on CLK while DATA is low: Ready to send.
@@ -654,7 +654,7 @@ class Decoder(srd.Decoder):
step = STEP_CLOCK_DATA_BITS step = STEP_CLOCK_DATA_BITS
ss_bit = self.samplenum ss_bit = self.samplenum
elif step == STEP_CLOCK_DATA_BITS: elif step == STEP_CLOCK_DATA_BITS:
if self.matched[1]: if self.matched & 0b10:
if clk == 1: if clk == 1:
# Rising edge on CLK; latch DATA. # Rising edge on CLK; latch DATA.
bits.append(data) bits.append(data)
@@ -671,6 +671,10 @@ class Decoder(srd.Decoder):
self.handle_eoi_change(False) self.handle_eoi_change(False)
step = STEP_WAIT_READY_TO_SEND step = STEP_WAIT_READY_TO_SEND
def check_bit(self, d):
v = self.matched & (1 << d)
return (v >> d) == 1
def decode_parallel(self, has_data_n, has_dav, has_atn, has_eoi, has_srq): def decode_parallel(self, has_data_n, has_dav, has_atn, has_eoi, has_srq):
if False in has_data_n or not has_dav or not has_atn: if False in has_data_n or not has_dav or not has_atn:
@@ -707,19 +711,19 @@ class Decoder(srd.Decoder):
# captures, many edges fall onto the same sample number. So # captures, many edges fall onto the same sample number. So
# we process active edges of flags early (before processing # we process active edges of flags early (before processing
# data bits), and inactive edges late (after data got processed). # data bits), and inactive edges late (after data got processed).
if idx_ifc is not None and self.matched[idx_ifc] and pins[PIN_IFC] == 1: if idx_ifc is not None and self.check_bit(idx_ifc) and pins[PIN_IFC] == 1:
self.handle_ifc_change(pins[PIN_IFC]) self.handle_ifc_change(pins[PIN_IFC])
if idx_eoi is not None and self.matched[idx_eoi] and pins[PIN_EOI] == 1: if idx_eoi is not None and self.check_bit(idx_eoi) and pins[PIN_EOI] == 1:
self.handle_eoi_change(pins[PIN_EOI]) self.handle_eoi_change(pins[PIN_EOI])
if self.matched[idx_atn] and pins[PIN_ATN] == 1: if self.check_bit(idx_atn) and pins[PIN_ATN] == 1:
self.handle_atn_change(pins[PIN_ATN]) self.handle_atn_change(pins[PIN_ATN])
if self.matched[idx_dav]: if self.check_bit(idx_dav):
self.handle_dav_change(pins[PIN_DAV], pins[PIN_DIO1:PIN_DIO8 + 1]) self.handle_dav_change(pins[PIN_DAV], pins[PIN_DIO1:PIN_DIO8 + 1])
if self.matched[idx_atn] and pins[PIN_ATN] == 0: if self.check_bit(idx_atn) and pins[PIN_ATN] == 0:
self.handle_atn_change(pins[PIN_ATN]) self.handle_atn_change(pins[PIN_ATN])
if idx_eoi is not None and self.matched[idx_eoi] and pins[PIN_EOI] == 0: if idx_eoi is not None and self.check_bit(idx_eoi) and pins[PIN_EOI] == 0:
self.handle_eoi_change(pins[PIN_EOI]) self.handle_eoi_change(pins[PIN_EOI])
if idx_ifc is not None and self.matched[idx_ifc] and pins[PIN_IFC] == 0: if idx_ifc is not None and self.check_bit(idx_ifc) and pins[PIN_IFC] == 0:
self.handle_ifc_change(pins[PIN_IFC]) self.handle_ifc_change(pins[PIN_IFC])
waitcond[idx_dav][PIN_DAV] = 'e' waitcond[idx_dav][PIN_DAV] = 'e'

2
libsigrokdecode4DSL/decoders/ir_rc6/pd.py
View File

@@ -146,7 +146,7 @@ class Decoder(srd.Decoder):
(self.ir,) = self.wait(conditions) (self.ir,) = self.wait(conditions)
if len(conditions) == 2: if len(conditions) == 2:
if self.matched[1]: if self.matched & 0b10:
self.state = 'IDLE' self.state = 'IDLE'
self.edges.append(self.samplenum) self.edges.append(self.samplenum)

8
libsigrokdecode4DSL/decoders/lfast/pd.py
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@@ -256,11 +256,15 @@ class Decoder(srd.Decoder):
self.put_payload() self.put_payload()
def decode(self): def decode(self):
bMoreMatch = False
while True: while True:
if self.timeout == 0: if self.timeout == 0:
rising_edge, = self.wait({0: 'e'}) rising_edge, = self.wait({0: 'e'})
bMoreMatch = False
else: else:
rising_edge, = self.wait([{0: 'e'}, {'skip': self.timeout}]) rising_edge, = self.wait([{0: 'e'}, {'skip': self.timeout}])
bMoreMatch = True
# If this is the first edge, we only update ss # If this is the first edge, we only update ss
if self.ss == 0: if self.ss == 0:
@@ -272,7 +276,7 @@ class Decoder(srd.Decoder):
self.es = self.samplenum self.es = self.samplenum
# Check for the sleep bit if this is a timeout condition # Check for the sleep bit if this is a timeout condition
if (len(self.matched) == 2) and self.matched[1]: if bMoreMatch and self.matched & 0b10 == 0b10:
rising_edge = ~rising_edge rising_edge = ~rising_edge
if self.state == state_sync: if self.state == state_sync:
self.reset() self.reset()
@@ -331,5 +335,5 @@ class Decoder(srd.Decoder):
# If we got here when a timeout occurred, we have processed all null # If we got here when a timeout occurred, we have processed all null
# bits that we could and should reset now to find the next packet # bits that we could and should reset now to find the next packet
if (len(self.matched) == 2) and self.matched[1]: if bMoreMatch and self.matched & 0b10 == 0b10:
self.reset() self.reset()

4
libsigrokdecode4DSL/decoders/pjdl/pd.py
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@@ -494,7 +494,7 @@ class Decoder(srd.Decoder):
curr_level, = self.wait([{PIN_DATA: 'e'}, {'skip': self.lookahead_width}]) curr_level, = self.wait([{PIN_DATA: 'e'}, {'skip': self.lookahead_width}])
self.carrier_check(curr_level, self.samplenum) self.carrier_check(curr_level, self.samplenum)
bit_level = curr_level bit_level = curr_level
edge_seen = self.matched[0] edge_seen = self.matched & 0b1
if edge_seen: if edge_seen:
bit_level = 1 - bit_level bit_level = 1 - bit_level
if not self.edges: if not self.edges:
@@ -687,7 +687,7 @@ class Decoder(srd.Decoder):
hold = self.hold_high_width hold = self.hold_high_width
curr_level, = self.wait([{PIN_DATA: 'l'}, {'skip': int(hold)}]) curr_level, = self.wait([{PIN_DATA: 'l'}, {'skip': int(hold)}])
self.carrier_check(curr_level, self.samplenum) self.carrier_check(curr_level, self.samplenum)
if self.matched[1]: if self.matched & 0b10:
self.edges.append(curr_snum) self.edges.append(curr_snum)
curr_level = 1 - curr_level curr_level = 1 - curr_level
curr_snum = self.samplenum curr_snum = self.samplenum

22
libsigrokdecode4DSL/decoders/sle44xx/pd.py
View File

@@ -443,6 +443,10 @@ class Decoder(srd.Decoder):
self.handle_data_byte(ss, es, data, bits) self.handle_data_byte(ss, es, data, bits)
def check_bit(self, d):
v = self.matched & (1 << d)
return (v >> d) == 1
def decode(self): def decode(self):
'''Decoder's main data interpretation loop.''' '''Decoder's main data interpretation loop.'''
@@ -493,31 +497,31 @@ class Decoder(srd.Decoder):
# Handle RESET conditions, including an optional CLK pulse # Handle RESET conditions, including an optional CLK pulse
# while RST is asserted. # while RST is asserted.
if self.matched[COND_RESET_START]: if self.check_bit(COND_RESET_START):
self.flush_queued() self.flush_queued()
ss_reset = self.samplenum ss_reset = self.samplenum
es_reset = ss_clk = es_clk = None es_reset = ss_clk = es_clk = None
continue continue
if self.matched[COND_RESET_STOP]: if self.check_bit(COND_RESET_STOP):
es_reset = self.samplenum es_reset = self.samplenum
self.handle_reset(ss_reset or 0, es_reset, ss_clk and es_clk) self.handle_reset(ss_reset or 0, es_reset, ss_clk and es_clk)
ss_reset = es_reset = ss_clk = es_clk = None ss_reset = es_reset = ss_clk = es_clk = None
continue continue
if self.matched[COND_RSTCLK_START]: if self.check_bit(COND_RSTCLK_START):
ss_clk = self.samplenum ss_clk = self.samplenum
es_clk = None es_clk = None
continue continue
if self.matched[COND_RSTCLK_STOP]: if self.check_bit(COND_RSTCLK_STOP):
es_clk = self.samplenum es_clk = self.samplenum
continue continue
# Handle data bits' validity boundaries. Also covers the # Handle data bits' validity boundaries. Also covers the
# periodic check for high I/O level and update of details # periodic check for high I/O level and update of details
# during internal processing. # during internal processing.
if self.matched[COND_DATA_START]: if self.check_bit(COND_DATA_START):
self.handle_data_bit(self.samplenum, None, io) self.handle_data_bit(self.samplenum, None, io)
continue continue
if self.matched[COND_DATA_STOP]: if self.check_bit(COND_DATA_STOP):
self.handle_data_bit(None, self.samplenum, None) self.handle_data_bit(None, self.samplenum, None)
continue continue
@@ -525,7 +529,7 @@ class Decoder(srd.Decoder):
# independent of CLK edges this time. This assures that the # independent of CLK edges this time. This assures that the
# decoder ends processing intervals as soon as possible, at # decoder ends processing intervals as soon as possible, at
# the most precise timestamp. # the most precise timestamp.
if is_processing and self.matched[COND_PROC_IOH]: if is_processing and self.check_bit(COND_PROC_IOH):
self.handle_data_bit(self.samplenum, self.samplenum, io) self.handle_data_bit(self.samplenum, self.samplenum, io)
continue continue
@@ -533,9 +537,9 @@ class Decoder(srd.Decoder):
# "outgoing data" or "internal processing" periods. This is # "outgoing data" or "internal processing" periods. This is
# what the data sheet specifies. # what the data sheet specifies.
if not is_outgoing and not is_processing: if not is_outgoing and not is_processing:
if self.matched[COND_CMD_START]: if self.check_bit(COND_CMD_START):
self.handle_command(self.samplenum, True) self.handle_command(self.samplenum, True)
continue continue
if self.matched[COND_CMD_STOP]: if self.check_bit(COND_CMD_STOP):
self.handle_command(self.samplenum, False) self.handle_command(self.samplenum, False)
continue continue