diff --git a/libsigrokdecode4DSL/decoders/a7105/pd.py b/libsigrokdecode4DSL/decoders/a7105/pd.py index d441c666..9a41d9f8 100644 --- a/libsigrokdecode4DSL/decoders/a7105/pd.py +++ b/libsigrokdecode4DSL/decoders/a7105/pd.py @@ -88,9 +88,7 @@ class Decoder(srd.Decoder): inputs = ['spi'] outputs = [] tags = ['IC', 'Wireless/RF'] - options = ( - {'id': 'hex_display', 'desc': 'Display payload in Hex', 'default': 'yes', - 'values': ('yes', 'no')}, + options = ( ) annotations = ( # Sent from the host to the chip. @@ -130,6 +128,9 @@ class Decoder(srd.Decoder): '''Put an annotation message 'msg' at 'pos'.''' self.put(pos[0], pos[1], self.out_ann, [ann, [msg]]) + def put_ann(self, pos, ann, msg_arr): + self.put(pos[0], pos[1], self.out_ann, [ann, msg_arr]) + def next(self): '''Resets the decoder after a complete command was decoded.''' # 'True' for the first byte after CS went low. @@ -253,24 +254,18 @@ class Decoder(srd.Decoder): True, all bytes are decoded as hex codes, otherwise only non printable characters are escaped.''' - if always_hex: - def escape(b): + def escape(b): return '{:02X}'.format(b) - else: - def escape(b): - c = chr(b) - if not str.isprintable(c): - return '\\x{:02X}'.format(b) - return c - data = ''.join([escape(b) for b in data]) - text = '{} = "{}"'.format(label, data.strip()) - self.putp(pos, ann, text) + data = ''.join([escape(b) for b in data]) + ann_arr = [label + ' = "{$}"', '@' + data] + + self.put_ann(pos, ann, ann_arr) def finish_command(self, pos): '''Decodes the remaining data bytes at position 'pos'.''' - - always_hex = self.options['hex_display'] == 'yes' + + always_hex = True if self.cmd == 'R_REGISTER': self.decode_register(pos, self.ann_cmd, self.dat, self.miso_bytes()) diff --git a/libsigrokdecode4DSL/decoders/ade77xx/pd.py b/libsigrokdecode4DSL/decoders/ade77xx/pd.py index 5a24a25e..74219eee 100644 --- a/libsigrokdecode4DSL/decoders/ade77xx/pd.py +++ b/libsigrokdecode4DSL/decoders/ade77xx/pd.py @@ -124,8 +124,8 @@ class Decoder(srd.Decoder): vali = self.miso_bytes[1] if write: - self.putx([1, ['%s: %#x' % (rblob[0], valo)]]) + self.putx([1, ['%s: {$}' % rblob[0], '@%02X' % valo]]) else: - self.putx([0, ['%s: %#x' % (rblob[0], vali)]]) + self.putx([0, ['%s: {$}' % rblob[0], '@%02X' % valo]]) self.reset_data() diff --git a/libsigrokdecode4DSL/decoders/caliper/pd.py b/libsigrokdecode4DSL/decoders/caliper/pd.py index 20a2a555..b9e5851f 100644 --- a/libsigrokdecode4DSL/decoders/caliper/pd.py +++ b/libsigrokdecode4DSL/decoders/caliper/pd.py @@ -91,7 +91,7 @@ class Decoder(srd.Decoder): # after inactivity for a user specified period. Present the # number of unprocessed bits to the user for diagnostics. clk, data = self.wait(wait_cond) - if timeout_ms and not self.matched[0]: + if timeout_ms and not self.matched & 0b1 == 0b1: if self.number_bits or self.flags_bits: count = len(self.number_bits) + len(self.flags_bits) self.putg(self.ss, self.samplenum, 1, [ diff --git a/libsigrokdecode4DSL/decoders/flexray/pd.py b/libsigrokdecode4DSL/decoders/flexray/pd.py index 8ec30439..fc52b95f 100644 --- a/libsigrokdecode4DSL/decoders/flexray/pd.py +++ b/libsigrokdecode4DSL/decoders/flexray/pd.py @@ -407,7 +407,7 @@ class Decoder(srd.Decoder): # Wait until we're in the correct bit/sampling position. pos = self.get_sample_point(self.curbit) (fr_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}]) - if self.matched[1]: + if self.matched & 0b10: self.dom_edge_seen() - if self.matched[0]: - self.handle_bit(fr_rx) + if self.matched & 0b01: + self.handle_bit(fr_rx) \ No newline at end of file diff --git a/libsigrokdecode4DSL/decoders/iec/pd.py b/libsigrokdecode4DSL/decoders/iec/pd.py index 8acd1d1f..13ac1bca 100644 --- a/libsigrokdecode4DSL/decoders/iec/pd.py +++ b/libsigrokdecode4DSL/decoders/iec/pd.py @@ -132,7 +132,7 @@ class Decoder(srd.Decoder): self.step = 0 if self.step == 0: - # Don't use self.matched[1] here since we might come from + # Don't use self.matched_[1] here since we might come from # a step with different conds due to the code above. if data == 0 and clk == 1: # Rising edge on CLK while DATA is low: Ready to send. diff --git a/libsigrokdecode4DSL/decoders/ieee488/pd.py b/libsigrokdecode4DSL/decoders/ieee488/pd.py index 4531cb30..5fb6fa88 100644 --- a/libsigrokdecode4DSL/decoders/ieee488/pd.py +++ b/libsigrokdecode4DSL/decoders/ieee488/pd.py @@ -624,12 +624,12 @@ class Decoder(srd.Decoder): data, clk = pins[PIN_DATA], pins[PIN_CLK] atn, = self.invert_pins([pins[PIN_ATN]]) - if self.matched[0]: + if self.matched & 0b1: # Falling edge on ATN, reset step. step = STEP_WAIT_READY_TO_SEND if step == STEP_WAIT_READY_TO_SEND: - # Don't use self.matched[1] here since we might come from + # Don't use self.matched_[1] here since we might come from # a step with different conds due to the code above. if data == 0 and clk == 1: # Rising edge on CLK while DATA is low: Ready to send. @@ -654,7 +654,7 @@ class Decoder(srd.Decoder): step = STEP_CLOCK_DATA_BITS ss_bit = self.samplenum elif step == STEP_CLOCK_DATA_BITS: - if self.matched[1]: + if self.matched & 0b10: if clk == 1: # Rising edge on CLK; latch DATA. bits.append(data) @@ -671,6 +671,10 @@ class Decoder(srd.Decoder): self.handle_eoi_change(False) step = STEP_WAIT_READY_TO_SEND + def check_bit(self, d): + v = self.matched & (1 << d) + return (v >> d) == 1 + def decode_parallel(self, has_data_n, has_dav, has_atn, has_eoi, has_srq): if False in has_data_n or not has_dav or not has_atn: @@ -707,19 +711,19 @@ class Decoder(srd.Decoder): # captures, many edges fall onto the same sample number. So # we process active edges of flags early (before processing # data bits), and inactive edges late (after data got processed). - if idx_ifc is not None and self.matched[idx_ifc] and pins[PIN_IFC] == 1: + if idx_ifc is not None and self.check_bit(idx_ifc) and pins[PIN_IFC] == 1: self.handle_ifc_change(pins[PIN_IFC]) - if idx_eoi is not None and self.matched[idx_eoi] and pins[PIN_EOI] == 1: + if idx_eoi is not None and self.check_bit(idx_eoi) and pins[PIN_EOI] == 1: self.handle_eoi_change(pins[PIN_EOI]) - if self.matched[idx_atn] and pins[PIN_ATN] == 1: + if self.check_bit(idx_atn) and pins[PIN_ATN] == 1: self.handle_atn_change(pins[PIN_ATN]) - if self.matched[idx_dav]: + if self.check_bit(idx_dav): self.handle_dav_change(pins[PIN_DAV], pins[PIN_DIO1:PIN_DIO8 + 1]) - if self.matched[idx_atn] and pins[PIN_ATN] == 0: + if self.check_bit(idx_atn) and pins[PIN_ATN] == 0: self.handle_atn_change(pins[PIN_ATN]) - if idx_eoi is not None and self.matched[idx_eoi] and pins[PIN_EOI] == 0: + if idx_eoi is not None and self.check_bit(idx_eoi) and pins[PIN_EOI] == 0: self.handle_eoi_change(pins[PIN_EOI]) - if idx_ifc is not None and self.matched[idx_ifc] and pins[PIN_IFC] == 0: + if idx_ifc is not None and self.check_bit(idx_ifc) and pins[PIN_IFC] == 0: self.handle_ifc_change(pins[PIN_IFC]) waitcond[idx_dav][PIN_DAV] = 'e' diff --git a/libsigrokdecode4DSL/decoders/ir_rc6/pd.py b/libsigrokdecode4DSL/decoders/ir_rc6/pd.py index e195dbd1..bd570173 100644 --- a/libsigrokdecode4DSL/decoders/ir_rc6/pd.py +++ b/libsigrokdecode4DSL/decoders/ir_rc6/pd.py @@ -146,7 +146,7 @@ class Decoder(srd.Decoder): (self.ir,) = self.wait(conditions) if len(conditions) == 2: - if self.matched[1]: + if self.matched & 0b10: self.state = 'IDLE' self.edges.append(self.samplenum) diff --git a/libsigrokdecode4DSL/decoders/lfast/pd.py b/libsigrokdecode4DSL/decoders/lfast/pd.py index 7476e59a..bd4c8ec4 100644 --- a/libsigrokdecode4DSL/decoders/lfast/pd.py +++ b/libsigrokdecode4DSL/decoders/lfast/pd.py @@ -256,11 +256,15 @@ class Decoder(srd.Decoder): self.put_payload() def decode(self): + bMoreMatch = False + while True: if self.timeout == 0: rising_edge, = self.wait({0: 'e'}) + bMoreMatch = False else: rising_edge, = self.wait([{0: 'e'}, {'skip': self.timeout}]) + bMoreMatch = True # If this is the first edge, we only update ss if self.ss == 0: @@ -272,7 +276,7 @@ class Decoder(srd.Decoder): self.es = self.samplenum # Check for the sleep bit if this is a timeout condition - if (len(self.matched) == 2) and self.matched[1]: + if bMoreMatch and self.matched & 0b10 == 0b10: rising_edge = ~rising_edge if self.state == state_sync: self.reset() @@ -331,5 +335,5 @@ class Decoder(srd.Decoder): # If we got here when a timeout occurred, we have processed all null # bits that we could and should reset now to find the next packet - if (len(self.matched) == 2) and self.matched[1]: + if bMoreMatch and self.matched & 0b10 == 0b10: self.reset() diff --git a/libsigrokdecode4DSL/decoders/pjdl/pd.py b/libsigrokdecode4DSL/decoders/pjdl/pd.py index d5cc39f2..b6adfe17 100644 --- a/libsigrokdecode4DSL/decoders/pjdl/pd.py +++ b/libsigrokdecode4DSL/decoders/pjdl/pd.py @@ -494,7 +494,7 @@ class Decoder(srd.Decoder): curr_level, = self.wait([{PIN_DATA: 'e'}, {'skip': self.lookahead_width}]) self.carrier_check(curr_level, self.samplenum) bit_level = curr_level - edge_seen = self.matched[0] + edge_seen = self.matched & 0b1 if edge_seen: bit_level = 1 - bit_level if not self.edges: @@ -687,7 +687,7 @@ class Decoder(srd.Decoder): hold = self.hold_high_width curr_level, = self.wait([{PIN_DATA: 'l'}, {'skip': int(hold)}]) self.carrier_check(curr_level, self.samplenum) - if self.matched[1]: + if self.matched & 0b10: self.edges.append(curr_snum) curr_level = 1 - curr_level curr_snum = self.samplenum diff --git a/libsigrokdecode4DSL/decoders/sle44xx/pd.py b/libsigrokdecode4DSL/decoders/sle44xx/pd.py index 9f332077..92842b3b 100644 --- a/libsigrokdecode4DSL/decoders/sle44xx/pd.py +++ b/libsigrokdecode4DSL/decoders/sle44xx/pd.py @@ -443,6 +443,10 @@ class Decoder(srd.Decoder): self.handle_data_byte(ss, es, data, bits) + def check_bit(self, d): + v = self.matched & (1 << d) + return (v >> d) == 1 + def decode(self): '''Decoder's main data interpretation loop.''' @@ -493,31 +497,31 @@ class Decoder(srd.Decoder): # Handle RESET conditions, including an optional CLK pulse # while RST is asserted. - if self.matched[COND_RESET_START]: + if self.check_bit(COND_RESET_START): self.flush_queued() ss_reset = self.samplenum es_reset = ss_clk = es_clk = None continue - if self.matched[COND_RESET_STOP]: + if self.check_bit(COND_RESET_STOP): es_reset = self.samplenum self.handle_reset(ss_reset or 0, es_reset, ss_clk and es_clk) ss_reset = es_reset = ss_clk = es_clk = None continue - if self.matched[COND_RSTCLK_START]: + if self.check_bit(COND_RSTCLK_START): ss_clk = self.samplenum es_clk = None continue - if self.matched[COND_RSTCLK_STOP]: + if self.check_bit(COND_RSTCLK_STOP): es_clk = self.samplenum continue # Handle data bits' validity boundaries. Also covers the # periodic check for high I/O level and update of details # during internal processing. - if self.matched[COND_DATA_START]: + if self.check_bit(COND_DATA_START): self.handle_data_bit(self.samplenum, None, io) continue - if self.matched[COND_DATA_STOP]: + if self.check_bit(COND_DATA_STOP): self.handle_data_bit(None, self.samplenum, None) continue @@ -525,7 +529,7 @@ class Decoder(srd.Decoder): # independent of CLK edges this time. This assures that the # decoder ends processing intervals as soon as possible, at # the most precise timestamp. - if is_processing and self.matched[COND_PROC_IOH]: + if is_processing and self.check_bit(COND_PROC_IOH): self.handle_data_bit(self.samplenum, self.samplenum, io) continue @@ -533,9 +537,9 @@ class Decoder(srd.Decoder): # "outgoing data" or "internal processing" periods. This is # what the data sheet specifies. if not is_outgoing and not is_processing: - if self.matched[COND_CMD_START]: + if self.check_bit(COND_CMD_START): self.handle_command(self.samplenum, True) continue - if self.matched[COND_CMD_STOP]: + if self.check_bit(COND_CMD_STOP): self.handle_command(self.samplenum, False) continue