forked from Ivasoft/openwrt
b3bdfd5df5
Assign the MDIO pins to the switch node instead of using pin hogging (where pins are assigned to the pin controller). This is the preferred way of assigning pins upstream. This converts amazonse, ar9 and vr9. danube is skipped because the pin controller doesn't define a pinmux for the MDIO pins (some of the SoC pads may be hardwired to the MDIO pins instead of being configurable). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
158 lines
2.8 KiB
Plaintext
158 lines
2.8 KiB
Plaintext
/dts-v1/;
|
|
|
|
#include "vr9.dtsi"
|
|
|
|
#include <dt-bindings/input/input.h>
|
|
#include <dt-bindings/mips/lantiq_rcu_gphy.h>
|
|
|
|
/ {
|
|
compatible = "arcadyan,vg3503j", "lantiq,xway", "lantiq,vr9";
|
|
model = "BT OpenReach VDSL Modem";
|
|
|
|
chosen {
|
|
bootargs = "console=ttyLTQ0,115200";
|
|
};
|
|
|
|
aliases {
|
|
led-boot = &power_green;
|
|
led-failsafe = &power_red;
|
|
led-running = &power_green;
|
|
led-upgrade = &power_green;
|
|
|
|
led-dsl = &dsl;
|
|
};
|
|
|
|
memory@0 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x2000000>;
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys-polled";
|
|
poll-interval = <100>;
|
|
reset {
|
|
label = "reset";
|
|
gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_RESTART>;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
power_red: power2 {
|
|
label = "vg3503j:red:power";
|
|
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
|
|
};
|
|
dsl: dsl {
|
|
label = "vg3503j:green:dsl";
|
|
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
|
|
};
|
|
power_green: power {
|
|
label = "vg3503j:green:power";
|
|
gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
|
|
default-state = "keep";
|
|
};
|
|
};
|
|
};
|
|
|
|
ð0 {
|
|
interface@0 {
|
|
compatible = "lantiq,xrx200-pdi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
|
|
lantiq,switch;
|
|
ethernet@2 {
|
|
compatible = "lantiq,xrx200-pdi-port";
|
|
reg = <2>;
|
|
phy-mode = "mii";
|
|
phy-handle = <&phy11>;
|
|
};
|
|
ethernet@4 {
|
|
compatible = "lantiq,xrx200-pdi-port";
|
|
reg = <4>;
|
|
phy-mode = "mii";
|
|
phy-handle = <&phy13>;
|
|
};
|
|
};
|
|
|
|
mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "lantiq,xrx200-mdio";
|
|
|
|
phy11: ethernet-phy@11 {
|
|
reg = <0x11>;
|
|
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
|
lantiq,led1h = <0x70>;
|
|
lantiq,led1l = <0x00>;
|
|
lantiq,led2h = <0x00>;
|
|
lantiq,led2l = <0x03>;
|
|
};
|
|
phy13: ethernet-phy@13 {
|
|
reg = <0x13>;
|
|
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
|
lantiq,led1h = <0x70>;
|
|
lantiq,led1l = <0x00>;
|
|
lantiq,led2h = <0x00>;
|
|
lantiq,led2l = <0x03>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&gphy0 {
|
|
lantiq,gphy-mode = <GPHY_MODE_GE>;
|
|
};
|
|
|
|
&gphy1 {
|
|
lantiq,gphy-mode = <GPHY_MODE_GE>;
|
|
};
|
|
|
|
&gpio {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&state_default>;
|
|
|
|
state_default: pinmux {
|
|
gphy-leds {
|
|
lantiq,groups = "gphy0 led0", "gphy0 led1",
|
|
"gphy0 led2", "gphy1 led0",
|
|
"gphy1 led1", "gphy1 led2";
|
|
lantiq,function = "gphy";
|
|
lantiq,pull = <2>;
|
|
lantiq,open-drain = <0>;
|
|
lantiq,output = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&localbus {
|
|
flash@0 {
|
|
compatible = "lantiq,nor";
|
|
bank-width = <2>;
|
|
reg = <0 0x0 0x2000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "uboot";
|
|
reg = <0x00000 0x20000>;
|
|
};
|
|
|
|
partition@20000 {
|
|
label = "firmware";
|
|
reg = <0x20000 0x7d0000>;
|
|
};
|
|
|
|
partition@7f0000 {
|
|
label = "uboot-env";
|
|
reg = <0x7f0000 0x10000>;
|
|
};
|
|
};
|
|
};
|
|
};
|