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openwrt/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7412.dts
Martin Blumenstingl b3bdfd5df5 lantiq: dts: assign the MDIO pins to the gsw node
Assign the MDIO pins to the switch node instead of using pin hogging
(where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.

This converts amazonse, ar9 and vr9. danube is skipped because the pin
controller doesn't define a pinmux for the MDIO pins (some of the SoC
pads may be hardwired to the MDIO pins instead of being configurable).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
2019-12-22 01:24:23 +01:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "vr9.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/mips/lantiq_rcu_gphy.h>
/ {
compatible = "avm,fritz7412", "lantiq,xway", "lantiq,vr9";
model = "AVM FRITZ!Box 7412";
chosen {
bootargs = "console=ttyLTQ0,115200";
};
aliases {
led-boot = &power_green;
led-failsafe = &power_red;
led-running = &power_green;
led-upgrade = &power_red;
led-dsl = &info;
led-wifi = &wifi;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x8000000>;
};
keys {
compatible = "gpio-keys-polled";
poll-interval = <100>;
wps {
label = "wps";
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
dect {
label = "dect";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PHONE>;
};
};
leds {
compatible = "gpio-leds";
power_green: power_green {
label = "fritz7412:green:power";
gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
power_red: power_red {
label = "fritz7412:red:power";
gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
};
fon {
label = "fritz7412:green:fon";
gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
};
dect {
label = "fritz7412:green:dect";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
wifi: wifi {
label = "fritz7412:green:wifi";
gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
};
info: info {
label = "fritz7412:green:info";
gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
};
};
};
&localbus {
flash@0 {
compatible = "lantiq,nand-xway";
bank-width = <2>;
reg = <0 0x0 0x2000000>;
lantiq,cs = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "urlader";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "nand-tffs";
reg = <0x40000 0x400000>;
read-only;
};
partition@440000 {
label = "kernel";
reg = <0x440000 0x400000>;
};
partition@840000 {
label = "ubi";
reg = <0x840000 0x3000000>;
};
partition@3840000 {
label = "reserved-kernel";
reg = <0x3840000 0x400000>;
read-only;
};
partition@3c40000 {
label = "reserved-filesystem";
reg = <0x3c40000 0x3000000>;
read-only;
};
partition@6c40000 {
label = "config";
reg = <0x6c40000 0x400000>;
read-only;
};
partition@6e40000 {
label = "nand-filesystem";
reg = <0x6e40000 0x400000>;
read-only;
};
};
};
};
&pcie0 {
status = "okay";
gpio-reset = <&gpio 11 GPIO_ACTIVE_HIGH>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
wifi@168c,002e {
compatible = "pci168c,002e";
reg = <0 0 0 0 0>;
qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */
};
};
};
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
pcie-rst {
lantiq,pins = "io11";
lantiq,open-drain = <1>;
lantiq,output = <1>;
};
nand-mux {
lantiq,groups = "nand cle", "nand ale",
"nand rd", "nand cs1",
"nand rdy";
lantiq,function = "ebu";
};
nand-pins {
lantiq,pins = "io13", "io24", "io49";
lantiq,pull = <1>;
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_FE>;
};
&eth0 {
lantiq,phys = <&gphy0>;
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mac-address = [ 00 11 22 33 44 55 ];
lantiq,switch;
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
};
&vmmc {
status = "okay";
};