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forked from Ivasoft/openwrt

ar71xx: fix QCA955X SGMII link loss

The QCA955X is affected by a hardware bug which causes link-loss of the
SGMII link between SoC and PHY. This happens on change of link-state or
speed.

It is not really known what causes this bug. It definitely occurs when
using a AR8033 Gigabit Ethernet PHY.

Qualcomm solves this Bug in a similar fashion. We need to apply the fix
on a per-device base via platform-data as performing the fixup work will
break connectivity in case the SGMII interface is connected to a Switch.

This bug was first proposed to be fixed by Sven Eckelmann in 2016.
 https://patchwork.ozlabs.org/patch/604782/

Based-on-patch-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Signed-off-by: David Bauer <mail@david-bauer.net>
This commit is contained in:
David Bauer
2018-08-06 16:15:04 +02:00
committed by John Crispin
parent fbe17867da
commit f4f99ec973
5 changed files with 127 additions and 0 deletions

View File

@@ -155,6 +155,7 @@ static void __init fritz450E_setup(void) {
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth0_data.phy_mask = BIT(FRITZ450E_PHY_ADDRESS);
ath79_eth0_data.enable_sgmii_fixup = 1;
ath79_eth0_pll_data.pll_1000 = 0x03000000;
ath79_eth0_pll_data.pll_100 = 0x00000101;
ath79_eth0_pll_data.pll_10 = 0x00001313;

View File

@@ -37,6 +37,7 @@ struct ag71xx_platform_data {
u8 is_ar724x:1;
u8 has_ar8216:1;
u8 use_flow_control:1;
u8 enable_sgmii_fixup:1;
u8 disable_inline_checksum_engine:1;
struct ag71xx_switch_platform_data *switch_data;