forked from Ivasoft/openwrt
ipq807x: rename target to qualcommax
Currently, ipq807x only covers Qualcomm IPQ807x SoC-s. However, Qualcomm also has IPQ60xx and IPQ50xx SoC-s under the AX WiSoC-s and they share a lot of stuff with IPQ807x, especially IPQ60xx so to avoid duplicating kernel patches and everything lets make a common target with per SoC subtargets. Start doing that by renaming ipq807x to qualcommax so that dependencies on ipq807x target can be updated. Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko
committed by
Christian Marangi
Christian Marangi
parent
de9955a62f
commit
f02f6aaa8d
22
target/linux/qualcommax/Makefile
Normal file
22
target/linux/qualcommax/Makefile
Normal file
@@ -0,0 +1,22 @@
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include $(TOPDIR)/rules.mk
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ARCH:=aarch64
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BOARD:=qualcommax
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BOARDNAME:=Qualcomm Atheros 802.11ax WiSoC-s
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FEATURES:=squashfs ramdisk fpu nand rtc emmc
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KERNELNAME:=Image dtbs
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CPU_TYPE:=cortex-a53
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SUBTARGETS:=generic
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KERNEL_PATCHVER:=6.1
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include $(INCLUDE_DIR)/target.mk
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DEFAULT_PACKAGES += \
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kmod-usb3 kmod-usb-dwc3 kmod-usb-dwc3-qcom \
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kmod-leds-gpio kmod-gpio-button-hotplug \
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kmod-phy-aquantia kmod-qca-nss-dp \
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ath11k-firmware-ipq8074 kmod-ath11k-ahb \
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wpad-basic-mbedtls uboot-envtools \
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e2fsprogs kmod-fs-ext4 losetup
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$(eval $(call BuildTarget))
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33
target/linux/qualcommax/base-files/etc/board.d/01_leds
Normal file
33
target/linux/qualcommax/base-files/etc/board.d/01_leds
Normal file
@@ -0,0 +1,33 @@
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. /lib/functions/uci-defaults.sh
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board_config_update
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board=$(board_name)
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case "$board" in
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edgecore,eap102)
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ucidef_set_led_netdev "wan" "WAN" "green:wanpoe" "wan"
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;;
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netgear,wax218)
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ucidef_set_led_netdev "lan" "LAN" "blue:lan" "lan"
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ucidef_set_led_wlan "wlan5g" "WIFI 5GHz" "blue:wlan5g" "phy0radio"
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ucidef_set_led_wlan "wlan2g" "WIFI 2.4GHz" "blue:wlan2g" "phy1radio"
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;;
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redmi,ax6|\
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xiaomi,ax3600)
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ucidef_set_led_netdev "wan" "WAN" "blue:network" "wan"
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;;
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qnap,301w)
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ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "lan1"
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ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "lan2"
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ucidef_set_led_netdev "lan3" "LAN3" "green:lan3" "lan3"
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ucidef_set_led_netdev "lan4" "LAN4" "green:lan4" "lan4"
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ucidef_set_led_netdev "10G_1" "10G_1" "green:10g_1" "10g-1"
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ucidef_set_led_netdev "10G_2" "10G_2" "green:10g_2" "10g-2"
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;;
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esac
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board_config_flush
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exit 0
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53
target/linux/qualcommax/base-files/etc/board.d/02_network
Normal file
53
target/linux/qualcommax/base-files/etc/board.d/02_network
Normal file
@@ -0,0 +1,53 @@
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#
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# Copyright (c) 2015 The Linux Foundation. All rights reserved.
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# Copyright (c) 2011-2015 OpenWrt.org
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#
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. /lib/functions/uci-defaults.sh
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. /lib/functions/system.sh
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ipq807x_setup_interfaces()
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{
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local board="$1"
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case "$board" in
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buffalo,wxr-5950ax12|\
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dynalink,dl-wrx36|\
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xiaomi,ax9000)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
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;;
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edgecore,eap102)
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ucidef_set_interfaces_lan_wan "lan" "wan"
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;;
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edimax,cax1800)
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ucidef_set_interfaces_lan_wan "lan"
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;;
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netgear,wax218)
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ucidef_set_interface_lan "lan" "dhcp"
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;;
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prpl,haze)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
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;;
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qnap,301w)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 10g-2" "10g-1"
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;;
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compex,wpq873|\
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redmi,ax6|\
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xiaomi,ax3600)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
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;;
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zyxel,nbg7815)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 10g" "wan"
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;;
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*)
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echo "Unsupported hardware. Network interfaces not initialized"
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;;
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esac
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}
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board_config_update
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board=$(board_name)
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ipq807x_setup_interfaces $board
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board_config_flush
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exit 0
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@@ -0,0 +1,44 @@
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#!/bin/sh
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[ -e /lib/firmware/$FIRMWARE ] && exit 0
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. /lib/functions/caldata.sh
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board=$(board_name)
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case "$FIRMWARE" in
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"ath11k/IPQ8074/hw2.0/cal-ahb-c000000.wifi.bin")
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case "$board" in
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buffalo,wxr-5950ax12|\
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compex,wpq873|\
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edgecore,eap102|\
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edimax,cax1800|\
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dynalink,dl-wrx36|\
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netgear,wax218|\
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qnap,301w|\
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redmi,ax6|\
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xiaomi,ax3600|\
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xiaomi,ax9000|\
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zyxel,nbg7815)
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caldata_extract "0:art" 0x1000 0x20000
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;;
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prpl,haze)
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caldata_extract_mmc "0:ART" 0x1000 0x20000
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;;
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esac
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;;
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"ath11k/QCN9074/hw1.0/cal-pci-0000:01:00.0.bin"|\
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"ath11k/QCN9074/hw1.0/cal-pci-0001:01:00.0.bin")
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case "$board" in
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prpl,haze)
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caldata_extract_mmc "0:ART" 0x26800 0x20000
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;;
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xiaomi,ax9000)
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caldata_extract "0:art" 0x26800 0x20000
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;;
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esac
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;;
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*)
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exit 1
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;;
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esac
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13
target/linux/qualcommax/base-files/etc/init.d/bootcount
Executable file
13
target/linux/qualcommax/base-files/etc/init.d/bootcount
Executable file
@@ -0,0 +1,13 @@
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#!/bin/sh /etc/rc.common
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START=99
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boot() {
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case $(board_name) in
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edgecore,eap102)
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fw_setenv upgrade_available 0
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# Unset changed flag after sysupgrade complete
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fw_setenv changed
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;;
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esac
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}
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55
target/linux/qualcommax/base-files/lib/upgrade/buffalo.sh
Normal file
55
target/linux/qualcommax/base-files/lib/upgrade/buffalo.sh
Normal file
@@ -0,0 +1,55 @@
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. /lib/functions.sh
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# Prepare UBI devices for OpenWrt installation
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# - rootfs (mtd22)
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# - remove "ubi_rootfs" volume (rootfs on stock)
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# - remove "fw_hash" volume (firmware hash)
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# - user_property (mtd24)
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# - remove "user_property_ubi" volume (user configuration)
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# - remove "extra_property" volume (gzipped syslog)
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buffalo_upgrade_prepare() {
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local ubi_rootdev ubi_propdev
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if ! ubi_rootdev="$(nand_attach_ubi rootfs)" || \
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! ubi_propdev="$(nand_attach_ubi user_property)"; then
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echo "failed to attach UBI volume \"rootfs\" or \"user_property\", rebooting..."
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reboot -f
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fi
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ubirmvol /dev/$ubi_rootdev -N ubi_rootfs &> /dev/null || true
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ubirmvol /dev/$ubi_rootdev -N fw_hash &> /dev/null || true
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ubirmvol /dev/$ubi_propdev -N user_property_ubi &> /dev/null || true
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ubirmvol /dev/$ubi_propdev -N extra_property &> /dev/null || true
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}
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# Re-create small dummy ubi_rootfs volume and update
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# fw_hash volume to pass the checking by U-Boot
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# - rootfs (mtd22)
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# - re-create "ubi_rootfs" volume
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# - re-create and update "fw_hash" volume
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# - rootfs_recover (mtd23)
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# - update "fw_hash" volume
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buffalo_upgrade_optvol() {
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local ubi_rootdev ubi_rcvrdev
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local hashvol_root hashvol_rcvr
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if ! ubi_rootdev="$(nand_attach_ubi rootfs)" || \
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! ubi_rcvrdev="$(nand_attach_ubi rootfs_recover)"; then
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echo "failed to attach UBI volume \"rootfs\" or \"rootfs_recover\", rebooting..."
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reboot -f
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fi
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ubimkvol /dev/$ubi_rootdev -N ubi_rootfs -S 1
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ubimkvol /dev/$ubi_rootdev -N fw_hash -S 1 -t static
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if ! hashvol_root="$(nand_find_volume $ubi_rootdev fw_hash)" || \
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! hashvol_rcvr="$(nand_find_volume $ubi_rcvrdev fw_hash)"; then
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echo "\"fw_hash\" volume in \"rootfs\" or \"rootfs_recover\" not found, rebooting..."
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reboot -f
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fi
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echo -n "00000000000000000000000000000000" > /tmp/dummyhash.txt
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ubiupdatevol /dev/$hashvol_root /tmp/dummyhash.txt
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ubiupdatevol /dev/$hashvol_rcvr /tmp/dummyhash.txt
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}
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83
target/linux/qualcommax/base-files/lib/upgrade/mmc.sh
Normal file
83
target/linux/qualcommax/base-files/lib/upgrade/mmc.sh
Normal file
@@ -0,0 +1,83 @@
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#
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# Copyright (C) 2016 lede-project.org
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#
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# this can be used as a generic mmc upgrade script
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# just add a device entry in platform.sh,
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# define "kernelname" and "rootfsname" and call mmc_do_upgrade
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# after the kernel and rootfs flash a loopdev (as overlay) is
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# setup on top of the rootfs partition
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# for the proper function a padded rootfs image is needed, basically
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# append "pad-to 64k" to the image definition
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# this is based on the ipq806x zyxel.sh mmc upgrade
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. /lib/functions.sh
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mmc_do_upgrade() {
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local tar_file="$1"
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local rootfs=
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local kernel=
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[ -z "$kernel" ] && kernel=$(find_mmc_part ${kernelname})
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[ -z "$rootfs" ] && rootfs=$(find_mmc_part ${rootfsname})
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[ -z "$kernel" ] && echo "Upgrade failed: kernel partition not found! Rebooting..." && reboot -f
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[ -z "$rootfs" ] && echo "Upgrade failed: rootfs partition not found! Rebooting..." && reboot -f
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mmc_do_flash $tar_file $kernel $rootfs
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return 0
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}
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mmc_do_flash() {
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local tar_file=$1
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local kernel=$2
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local rootfs=$3
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# keep sure its unbound
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losetup --detach-all || {
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echo Failed to detach all loop devices. Skip this try.
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reboot -f
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}
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# use the first found directory in the tar archive
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local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
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board_dir=${board_dir%/}
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echo "flashing kernel to $kernel"
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tar xf $tar_file ${board_dir}/kernel -O >$kernel
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echo "flashing rootfs to ${rootfs}"
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tar xf $tar_file ${board_dir}/root -O >"${rootfs}"
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# a padded rootfs is needed for overlay fs creation
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local offset=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
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[ $offset -lt 65536 ] && {
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echo Wrong size for rootfs: $offset
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sleep 10
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reboot -f
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}
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# Mount loop for rootfs_data
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local loopdev="$(losetup -f)"
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losetup -o $offset $loopdev $rootfs || {
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echo "Failed to mount looped rootfs_data."
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sleep 10
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reboot -f
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}
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echo "Format new rootfs_data at position ${offset}."
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mkfs.ext4 -F -L rootfs_data $loopdev
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mkdir /tmp/new_root
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mount -t ext4 $loopdev /tmp/new_root && {
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echo "Saving config to rootfs_data at position ${offset}."
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cp -v "$UPGRADE_BACKUP" "/tmp/new_root/$BACKUP_FILE"
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umount /tmp/new_root
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}
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# Cleanup
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losetup -d $loopdev >/dev/null 2>&1
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sync
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umount -a
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reboot -f
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}
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117
target/linux/qualcommax/base-files/lib/upgrade/platform.sh
Normal file
117
target/linux/qualcommax/base-files/lib/upgrade/platform.sh
Normal file
@@ -0,0 +1,117 @@
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PART_NAME=firmware
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REQUIRE_IMAGE_METADATA=1
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RAMFS_COPY_BIN='fw_printenv fw_setenv head'
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RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
|
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|
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xiaomi_initramfs_prepare() {
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# Wipe UBI if running initramfs
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[ "$(rootfs_type)" = "tmpfs" ] || return 0
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local rootfs_mtdnum="$( find_mtd_index rootfs )"
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if [ ! "$rootfs_mtdnum" ]; then
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echo "unable to find mtd partition rootfs"
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return 1
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fi
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|
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local kern_mtdnum="$( find_mtd_index ubi_kernel )"
|
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if [ ! "$kern_mtdnum" ]; then
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echo "unable to find mtd partition ubi_kernel"
|
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return 1
|
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fi
|
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|
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ubidetach -m "$rootfs_mtdnum"
|
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ubiformat /dev/mtd$rootfs_mtdnum -y
|
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|
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ubidetach -m "$kern_mtdnum"
|
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ubiformat /dev/mtd$kern_mtdnum -y
|
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}
|
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|
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platform_check_image() {
|
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return 0;
|
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}
|
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|
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platform_pre_upgrade() {
|
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case "$(board_name)" in
|
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redmi,ax6|\
|
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xiaomi,ax3600|\
|
||||
xiaomi,ax9000)
|
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xiaomi_initramfs_prepare
|
||||
;;
|
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esac
|
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}
|
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|
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platform_do_upgrade() {
|
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case "$(board_name)" in
|
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buffalo,wxr-5950ax12)
|
||||
CI_KERN_UBIPART="rootfs"
|
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CI_ROOT_UBIPART="user_property"
|
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buffalo_upgrade_prepare
|
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nand_do_flash_file "$1" || nand_do_upgrade_failed
|
||||
nand_do_restore_config || nand_do_upgrade_failed
|
||||
buffalo_upgrade_optvol
|
||||
;;
|
||||
dynalink,dl-wrx36)
|
||||
nand_do_upgrade "$1"
|
||||
;;
|
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edgecore,eap102)
|
||||
active="$(fw_printenv -n active)"
|
||||
if [ "$active" -eq "1" ]; then
|
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CI_UBIPART="rootfs2"
|
||||
else
|
||||
CI_UBIPART="rootfs1"
|
||||
fi
|
||||
# force altbootcmd which handles partition change in u-boot
|
||||
fw_setenv bootcount 3
|
||||
fw_setenv upgrade_available 1
|
||||
nand_do_upgrade "$1"
|
||||
;;
|
||||
compex,wpq873|\
|
||||
edimax,cax1800|\
|
||||
netgear,wax218)
|
||||
nand_do_upgrade "$1"
|
||||
;;
|
||||
prpl,haze|\
|
||||
qnap,301w)
|
||||
kernelname="0:HLOS"
|
||||
rootfsname="rootfs"
|
||||
mmc_do_upgrade "$1"
|
||||
;;
|
||||
zyxel,nbg7815)
|
||||
local config_mtdnum="$(find_mtd_index 0:bootconfig)"
|
||||
[ -z "$config_mtdnum" ] && reboot
|
||||
part_num="$(hexdump -e '1/1 "%01x|"' -n 1 -s 168 -C /dev/mtd$config_mtdnum | cut -f 1 -d "|" | head -n1)"
|
||||
if [ "$part_num" -eq "0" ]; then
|
||||
kernelname="0:HLOS"
|
||||
rootfsname="rootfs"
|
||||
mmc_do_upgrade "$1"
|
||||
else
|
||||
kernelname="0:HLOS_1"
|
||||
rootfsname="rootfs_1"
|
||||
mmc_do_upgrade "$1"
|
||||
fi
|
||||
;;
|
||||
redmi,ax6|\
|
||||
xiaomi,ax3600|\
|
||||
xiaomi,ax9000)
|
||||
# Make sure that UART is enabled
|
||||
fw_setenv boot_wait on
|
||||
fw_setenv uart_en 1
|
||||
|
||||
# Enforce single partition.
|
||||
fw_setenv flag_boot_rootfs 0
|
||||
fw_setenv flag_last_success 0
|
||||
fw_setenv flag_boot_success 1
|
||||
fw_setenv flag_try_sys1_failed 8
|
||||
fw_setenv flag_try_sys2_failed 8
|
||||
|
||||
# Kernel and rootfs are placed in 2 different UBI
|
||||
CI_KERN_UBIPART="ubi_kernel"
|
||||
CI_ROOT_UBIPART="rootfs"
|
||||
nand_do_upgrade "$1"
|
||||
;;
|
||||
*)
|
||||
default_do_upgrade "$1"
|
||||
;;
|
||||
esac
|
||||
}
|
||||
560
target/linux/qualcommax/config-6.1
Normal file
560
target/linux/qualcommax/config-6.1
Normal file
@@ -0,0 +1,560 @@
|
||||
CONFIG_64BIT=y
|
||||
# CONFIG_APQ_GCC_8084 is not set
|
||||
# CONFIG_APQ_MMCC_8084 is not set
|
||||
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
|
||||
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_FORCE_MAX_ORDER=11
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
||||
CONFIG_ARCH_NR_GPIO=0
|
||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
||||
CONFIG_ARCH_QCOM=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_STACKWALK=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_WANTS_NO_INSTR=y
|
||||
CONFIG_ARCH_WANTS_THP_SWAP=y
|
||||
CONFIG_ARM64=y
|
||||
CONFIG_ARM64_4K_PAGES=y
|
||||
CONFIG_ARM64_ERRATUM_1165522=y
|
||||
CONFIG_ARM64_ERRATUM_1286807=y
|
||||
CONFIG_ARM64_ERRATUM_2051678=y
|
||||
CONFIG_ARM64_ERRATUM_2054223=y
|
||||
CONFIG_ARM64_ERRATUM_2067961=y
|
||||
CONFIG_ARM64_ERRATUM_2077057=y
|
||||
CONFIG_ARM64_ERRATUM_2658417=y
|
||||
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
|
||||
CONFIG_ARM64_PAGE_SHIFT=12
|
||||
CONFIG_ARM64_PA_BITS=48
|
||||
CONFIG_ARM64_PA_BITS_48=y
|
||||
CONFIG_ARM64_PTR_AUTH=y
|
||||
CONFIG_ARM64_PTR_AUTH_KERNEL=y
|
||||
CONFIG_ARM64_SME=y
|
||||
CONFIG_ARM64_SVE=y
|
||||
CONFIG_ARM64_TAGGED_ADDR_ABI=y
|
||||
CONFIG_ARM64_VA_BITS=39
|
||||
CONFIG_ARM64_VA_BITS_39=y
|
||||
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
|
||||
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
|
||||
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
|
||||
CONFIG_ARM_AMBA=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_GIC_V2M=y
|
||||
CONFIG_ARM_GIC_V3=y
|
||||
CONFIG_ARM_GIC_V3_ITS=y
|
||||
CONFIG_ARM_GIC_V3_ITS_PCI=y
|
||||
# CONFIG_ARM_MHU_V2 is not set
|
||||
CONFIG_ARM_PSCI_CPUIDLE=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
|
||||
CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
|
||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BLK_MQ_VIRTIO=y
|
||||
CONFIG_BLK_PM=y
|
||||
CONFIG_CAVIUM_TX2_ERRATUM_219=y
|
||||
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
|
||||
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
|
||||
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
|
||||
CONFIG_CC_NO_ARRAY_BOUNDS=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_COMMON_CLK_QCOM=y
|
||||
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
|
||||
# CONFIG_COMPAT_32BIT_TIME is not set
|
||||
CONFIG_CONTEXT_TRACKING=y
|
||||
CONFIG_CONTEXT_TRACKING_IDLE=y
|
||||
CONFIG_COREDUMP=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
||||
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
|
||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_FREQ_THERMAL=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_CPU_IDLE_GOV_MENU=y
|
||||
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_CPU_PM=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_CRC8=y
|
||||
CONFIG_CRYPTO_AUTHENC=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_DEV_QCE=y
|
||||
CONFIG_CRYPTO_DEV_QCE_AEAD=y
|
||||
# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
|
||||
CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
|
||||
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
|
||||
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
|
||||
CONFIG_CRYPTO_DEV_QCE_SHA=y
|
||||
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
|
||||
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
|
||||
CONFIG_CRYPTO_DEV_QCOM_RNG=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_HASH_INFO=y
|
||||
CONFIG_CRYPTO_HW=y
|
||||
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
|
||||
CONFIG_CRYPTO_LIB_DES=y
|
||||
CONFIG_CRYPTO_LIB_SHA1=y
|
||||
CONFIG_CRYPTO_LIB_SHA256=y
|
||||
CONFIG_CRYPTO_LIB_UTILS=y
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
|
||||
CONFIG_CRYPTO_RNG=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
|
||||
# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
|
||||
CONFIG_CRYPTO_XTS=y
|
||||
CONFIG_CRYPTO_ZSTD=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEV_COREDUMP=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_OF=y
|
||||
CONFIG_DMA_VIRTUAL_CHANNELS=y
|
||||
CONFIG_DTC=y
|
||||
CONFIG_DT_IDLE_GENPD=y
|
||||
CONFIG_DT_IDLE_STATES=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_FUJITSU_ERRATUM_010001=y
|
||||
CONFIG_FWNODE_MDIO=y
|
||||
CONFIG_FW_LOADER_PAGED_BUF=y
|
||||
CONFIG_FW_LOADER_SYSFS=y
|
||||
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
|
||||
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_CPU_VULNERABILITIES=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_GETTIMEOFDAY=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IOREMAP=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_GENERIC_PINCTRL_GROUPS=y
|
||||
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HWSPINLOCK_QCOM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
# CONFIG_I2C_QCOM_CCI is not set
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_IIO=y
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_IPQ_APSS_6018=y
|
||||
CONFIG_IPQ_APSS_PLL=y
|
||||
# CONFIG_IPQ_GCC_4019 is not set
|
||||
# CONFIG_IPQ_GCC_6018 is not set
|
||||
# CONFIG_IPQ_GCC_806X is not set
|
||||
CONFIG_IPQ_GCC_8074=y
|
||||
# CONFIG_IPQ_LCC_806X is not set
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
# CONFIG_KPSS_XCC is not set
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_DEVRES=y
|
||||
CONFIG_MDIO_IPQ4019=y
|
||||
# CONFIG_MDM_GCC_9615 is not set
|
||||
# CONFIG_MDM_LCC_9615 is not set
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
# CONFIG_MFD_HI6421_SPMI is not set
|
||||
# CONFIG_MFD_QCOM_RPM is not set
|
||||
CONFIG_MFD_SPMI_PMIC=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
|
||||
CONFIG_MMC_SDHCI_MSM=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
# CONFIG_MSM_GCC_8660 is not set
|
||||
# CONFIG_MSM_GCC_8909 is not set
|
||||
# CONFIG_MSM_GCC_8916 is not set
|
||||
# CONFIG_MSM_GCC_8939 is not set
|
||||
# CONFIG_MSM_GCC_8960 is not set
|
||||
# CONFIG_MSM_GCC_8974 is not set
|
||||
# CONFIG_MSM_GCC_8976 is not set
|
||||
# CONFIG_MSM_GCC_8994 is not set
|
||||
# CONFIG_MSM_GCC_8996 is not set
|
||||
# CONFIG_MSM_GCC_8998 is not set
|
||||
# CONFIG_MSM_GPUCC_8998 is not set
|
||||
# CONFIG_MSM_LCC_8960 is not set
|
||||
# CONFIG_MSM_MMCC_8960 is not set
|
||||
# CONFIG_MSM_MMCC_8974 is not set
|
||||
# CONFIG_MSM_MMCC_8996 is not set
|
||||
# CONFIG_MSM_MMCC_8998 is not set
|
||||
CONFIG_MTD_NAND_CORE=y
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
||||
CONFIG_MTD_NAND_QCOM=y
|
||||
CONFIG_MTD_QCOMSMEM_PARTS=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_SELFTESTS=y
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=4
|
||||
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVMEM_QCOM_QFPROM=y
|
||||
# CONFIG_NVMEM_SPMI_SDAM is not set
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVMEM_U_BOOT_ENV=y
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCIE_QCOM=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PGTABLE_LEVELS=3
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
|
||||
# CONFIG_PHY_QCOM_EDP is not set
|
||||
# CONFIG_PHY_QCOM_IPQ4019_USB is not set
|
||||
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
|
||||
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
|
||||
# CONFIG_PHY_QCOM_PCIE2 is not set
|
||||
CONFIG_PHY_QCOM_QMP=y
|
||||
CONFIG_PHY_QCOM_QUSB2=y
|
||||
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
|
||||
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
|
||||
# CONFIG_PHY_QCOM_USB_SS is not set
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_IPQ6018 is not set
|
||||
CONFIG_PINCTRL_IPQ8074=y
|
||||
CONFIG_PINCTRL_MSM=y
|
||||
# CONFIG_PINCTRL_MSM8916 is not set
|
||||
# CONFIG_PINCTRL_MSM8976 is not set
|
||||
# CONFIG_PINCTRL_MSM8994 is not set
|
||||
# CONFIG_PINCTRL_MSM8996 is not set
|
||||
# CONFIG_PINCTRL_MSM8998 is not set
|
||||
# CONFIG_PINCTRL_QCM2290 is not set
|
||||
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
|
||||
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
|
||||
# CONFIG_PINCTRL_QCS404 is not set
|
||||
# CONFIG_PINCTRL_SC7180 is not set
|
||||
# CONFIG_PINCTRL_SC8280XP is not set
|
||||
# CONFIG_PINCTRL_SDM660 is not set
|
||||
# CONFIG_PINCTRL_SDM845 is not set
|
||||
# CONFIG_PINCTRL_SM6350 is not set
|
||||
# CONFIG_PINCTRL_SM6375 is not set
|
||||
# CONFIG_PINCTRL_SM8150 is not set
|
||||
# CONFIG_PINCTRL_SM8250 is not set
|
||||
# CONFIG_PINCTRL_SM8450 is not set
|
||||
CONFIG_PM=y
|
||||
# CONFIG_PM8916_WATCHDOG is not set
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
|
||||
CONFIG_POWER_RESET=y
|
||||
# CONFIG_POWER_RESET_MSM is not set
|
||||
# CONFIG_POWER_RESET_QCOM_PON is not set
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_PREEMPT_NONE_BUILD=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
||||
# CONFIG_QCM_DISPCC_2290 is not set
|
||||
# CONFIG_QCM_GCC_2290 is not set
|
||||
# CONFIG_QCOM_A53PLL is not set
|
||||
# CONFIG_QCOM_AOSS_QMP is not set
|
||||
CONFIG_QCOM_APCS_IPC=y
|
||||
CONFIG_QCOM_APM=y
|
||||
# CONFIG_QCOM_APR is not set
|
||||
CONFIG_QCOM_BAM_DMA=y
|
||||
# CONFIG_QCOM_CLK_APCC_MSM8996 is not set
|
||||
# CONFIG_QCOM_CLK_APCS_MSM8916 is not set
|
||||
# CONFIG_QCOM_CLK_APCS_SDX55 is not set
|
||||
# CONFIG_QCOM_COINCELL is not set
|
||||
# CONFIG_QCOM_COMMAND_DB is not set
|
||||
# CONFIG_QCOM_CPR is not set
|
||||
# CONFIG_QCOM_EBI2 is not set
|
||||
# CONFIG_QCOM_FASTRPC is not set
|
||||
CONFIG_QCOM_GDSC=y
|
||||
# CONFIG_QCOM_GENI_SE is not set
|
||||
# CONFIG_QCOM_GSBI is not set
|
||||
# CONFIG_QCOM_HFPLL is not set
|
||||
# CONFIG_QCOM_ICC_BWMON is not set
|
||||
# CONFIG_QCOM_IPCC is not set
|
||||
# CONFIG_QCOM_LLCC is not set
|
||||
CONFIG_QCOM_MDT_LOADER=y
|
||||
# CONFIG_QCOM_MPM is not set
|
||||
# CONFIG_QCOM_OCMEM is not set
|
||||
# CONFIG_QCOM_PDC is not set
|
||||
CONFIG_QCOM_PIL_INFO=y
|
||||
# CONFIG_QCOM_Q6V5_ADSP is not set
|
||||
CONFIG_QCOM_Q6V5_COMMON=y
|
||||
# CONFIG_QCOM_Q6V5_MSS is not set
|
||||
# CONFIG_QCOM_Q6V5_PAS is not set
|
||||
CONFIG_QCOM_Q6V5_WCSS=y
|
||||
# CONFIG_QCOM_RMTFS_MEM is not set
|
||||
# CONFIG_QCOM_RPMH is not set
|
||||
CONFIG_QCOM_RPROC_COMMON=y
|
||||
CONFIG_QCOM_SCM=y
|
||||
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
|
||||
# CONFIG_QCOM_SMD_RPM is not set
|
||||
CONFIG_QCOM_SMEM=y
|
||||
CONFIG_QCOM_SMEM_STATE=y
|
||||
CONFIG_QCOM_SMP2P=y
|
||||
# CONFIG_QCOM_SMSM is not set
|
||||
CONFIG_QCOM_SOCINFO=y
|
||||
# CONFIG_QCOM_SPM is not set
|
||||
CONFIG_QCOM_SPMI_ADC5=y
|
||||
# CONFIG_QCOM_SPMI_RRADC is not set
|
||||
# CONFIG_QCOM_STATS is not set
|
||||
# CONFIG_QCOM_SYSMON is not set
|
||||
CONFIG_QCOM_TSENS=y
|
||||
CONFIG_QCOM_VADC_COMMON=y
|
||||
# CONFIG_QCOM_WCNSS_CTRL is not set
|
||||
# CONFIG_QCOM_WCNSS_PIL is not set
|
||||
CONFIG_QCOM_WDT=y
|
||||
# CONFIG_QCS_GCC_404 is not set
|
||||
# CONFIG_QCS_Q6SSTOP_404 is not set
|
||||
# CONFIG_QCS_TURING_404 is not set
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_RANDSTRUCT_NONE=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGMAP_SPMI=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_CPR3=y
|
||||
# CONFIG_REGULATOR_CPR3_NPU is not set
|
||||
CONFIG_REGULATOR_CPR4_APSS=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
# CONFIG_REGULATOR_QCOM_LABIBB is not set
|
||||
CONFIG_REGULATOR_QCOM_SPMI=y
|
||||
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
|
||||
# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_REMOTEPROC=y
|
||||
CONFIG_REMOTEPROC_CDEV=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
# CONFIG_RESET_QCOM_AOSS is not set
|
||||
# CONFIG_RESET_QCOM_PDC is not set
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPMSG=y
|
||||
CONFIG_RPMSG_CHAR=y
|
||||
# CONFIG_RPMSG_CTRL is not set
|
||||
# CONFIG_RPMSG_NS is not set
|
||||
CONFIG_RPMSG_QCOM_GLINK=y
|
||||
CONFIG_RPMSG_QCOM_GLINK_RPM=y
|
||||
CONFIG_RPMSG_QCOM_GLINK_SMEM=y
|
||||
CONFIG_RPMSG_QCOM_SMD=y
|
||||
# CONFIG_RPMSG_TTY is not set
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_PM8XXX=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
# CONFIG_SCHED_CORE is not set
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCHED_SMT=y
|
||||
CONFIG_SCHED_THERMAL_PRESSURE=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_COMMON=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
# CONFIG_SC_CAMCC_7280 is not set
|
||||
# CONFIG_SC_DISPCC_7180 is not set
|
||||
# CONFIG_SC_GCC_7180 is not set
|
||||
# CONFIG_SC_GCC_8280XP is not set
|
||||
# CONFIG_SC_GPUCC_7180 is not set
|
||||
# CONFIG_SC_LPASSCC_7280 is not set
|
||||
# CONFIG_SC_LPASS_CORECC_7180 is not set
|
||||
# CONFIG_SC_LPASS_CORECC_7280 is not set
|
||||
# CONFIG_SC_MSS_7180 is not set
|
||||
# CONFIG_SC_VIDEOCC_7180 is not set
|
||||
# CONFIG_SDM_CAMCC_845 is not set
|
||||
# CONFIG_SDM_DISPCC_845 is not set
|
||||
# CONFIG_SDM_GCC_660 is not set
|
||||
# CONFIG_SDM_GCC_845 is not set
|
||||
# CONFIG_SDM_GPUCC_845 is not set
|
||||
# CONFIG_SDM_LPASSCC_845 is not set
|
||||
# CONFIG_SDM_VIDEOCC_845 is not set
|
||||
# CONFIG_SDX_GCC_65 is not set
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SMP=y
|
||||
# CONFIG_SM_CAMCC_8450 is not set
|
||||
# CONFIG_SM_GCC_8150 is not set
|
||||
# CONFIG_SM_GCC_8250 is not set
|
||||
# CONFIG_SM_GCC_8450 is not set
|
||||
# CONFIG_SM_GPUCC_6350 is not set
|
||||
# CONFIG_SM_GPUCC_8150 is not set
|
||||
# CONFIG_SM_GPUCC_8250 is not set
|
||||
# CONFIG_SM_GPUCC_8350 is not set
|
||||
# CONFIG_SM_VIDEOCC_8150 is not set
|
||||
# CONFIG_SM_VIDEOCC_8250 is not set
|
||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||
CONFIG_SOC_BUS=y
|
||||
CONFIG_SOFTIRQ_ON_OWN_STACK=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPMI=y
|
||||
# CONFIG_SPMI_HISI3670 is not set
|
||||
CONFIG_SPMI_MSM_PMIC_ARB=y
|
||||
# CONFIG_SPMI_PMIC_CLKDIV is not set
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTIO_ANCHOR=y
|
||||
# CONFIG_VIRTIO_BLK is not set
|
||||
# CONFIG_VIRTIO_NET is not set
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_WANT_DEV_COREDUMP=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_WATCHDOG_SYSFS=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
CONFIG_ZSTD_COMMON=y
|
||||
CONFIG_ZSTD_COMPRESS=y
|
||||
CONFIG_ZSTD_DECOMPRESS=y
|
||||
@@ -0,0 +1,322 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/* Copyright (c) 2021, Dirk Buchwalder <buchwalder@posteo.de> */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8074-512m.dtsi"
|
||||
#include "ipq8074-ac-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Edimax CAX1800";
|
||||
compatible = "edimax,cax1800", "qcom,ipq8074";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
led-boot = &led_system_red;
|
||||
led-failsafe = &led_system_red;
|
||||
led-running = &led_system_green;
|
||||
led-upgrade = &led_system_red;
|
||||
/* Aliases as required by u-boot to patch MAC addresses */
|
||||
ethernet0 = &dp5;
|
||||
label-mac-device = &dp5;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs-append = " root=/dev/ubiblock0_1";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_system_red: system-red {
|
||||
label = "red:system";
|
||||
gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_system_green: system-green {
|
||||
label = "green:system";
|
||||
gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_system_blue: system-blue {
|
||||
label = "blue:system";
|
||||
gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-pins {
|
||||
mdc {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&prng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "rootfs";
|
||||
reg = <0x0000000 0x3400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
cs-select = <0>;
|
||||
status = "ok";
|
||||
|
||||
m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
use-default-sizes;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "0:sbl1";
|
||||
reg = <0x0 0x50000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@50000 {
|
||||
label = "0:mibib";
|
||||
reg = <0x50000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "0:bootconfig";
|
||||
reg = <0x60000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "0:bootconfig1";
|
||||
reg = <0x80000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@a0000 {
|
||||
label = "0:qsee";
|
||||
reg = <0xa0000 0x180000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@220000 {
|
||||
label = "0:qsee_1";
|
||||
reg = <0x220000 0x180000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3a0000 {
|
||||
label = "0:devcfg";
|
||||
reg = <0x3a0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3b0000 {
|
||||
label = "0:devcfg_1";
|
||||
reg = <0x3b0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3c0000 {
|
||||
label = "0:apdp";
|
||||
reg = <0x3c0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3d0000 {
|
||||
label = "0:apdp_1";
|
||||
reg = <0x3d0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3e0000 {
|
||||
label = "0:rpm";
|
||||
reg = <0x3e0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@420000 {
|
||||
label = "0:rpm_1";
|
||||
reg = <0x420000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@460000 {
|
||||
label = "0:cdt";
|
||||
reg = <0x460000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@470000 {
|
||||
label = "0:cdt_1";
|
||||
reg = <0x470000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@480000 {
|
||||
label = "0:appsblenv";
|
||||
reg = <0x480000 0x10000>;
|
||||
};
|
||||
|
||||
partition@490000 {
|
||||
label = "0:appsbl";
|
||||
reg = <0x490000 0xa0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@530000 {
|
||||
label = "0:appsbl_1";
|
||||
reg = <0x530000 0xa0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@5d0000 {
|
||||
label = "0:art";
|
||||
reg = <0x5d0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@610000 {
|
||||
label = "0:ethphyfw";
|
||||
reg = <0x610000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
|
||||
|
||||
qca8075: ethernet-phy@4 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
|
||||
switch_lan_bmp = <0x1e>; /* lan port bitmap */
|
||||
switch_wan_bmp = <0x20>; /* wan port bitmap */
|
||||
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
|
||||
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
|
||||
switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
|
||||
bm_tick_mode = <0>; /* bm tick mode */
|
||||
tm_tick_mode = <0>; /* tm tick mode */
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@0 {
|
||||
port_id = <1>;
|
||||
phy_address = <0>;
|
||||
};
|
||||
port@1 {
|
||||
port_id = <2>;
|
||||
phy_address = <1>;
|
||||
};
|
||||
port@2 {
|
||||
port_id = <3>;
|
||||
phy_address = <2>;
|
||||
};
|
||||
port@3 {
|
||||
port_id = <4>;
|
||||
phy_address = <3>;
|
||||
};
|
||||
port@4 {
|
||||
port_id = <5>;
|
||||
phy_address = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp5 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075>;
|
||||
label = "lan";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
qcom,ath11k-calibration-variant = "Edimax-CAX1800";
|
||||
qcom,ath11k-fw-memory-mode = <1>;
|
||||
};
|
||||
@@ -0,0 +1,73 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8071-ax3600.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Xiaomi AX3600";
|
||||
compatible = "xiaomi,ax3600", "qcom,ipq8074";
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_system_blue: system-blue {
|
||||
label = "blue:system";
|
||||
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_system_yellow: system-yellow {
|
||||
label = "yellow:system";
|
||||
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
network-yellow {
|
||||
label = "yellow:network";
|
||||
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
network-blue {
|
||||
label = "blue:network";
|
||||
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
aiot {
|
||||
label = "blue:aiot";
|
||||
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy0tpt";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_qmp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
|
||||
perst-gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
wifi0: wifi@1,0 {
|
||||
status = "okay";
|
||||
|
||||
compatible = "qcom,ath10k";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
|
||||
qcom,ath10k-calibration-variant = "Xiaomi-AX3600";
|
||||
nvmem-cell-names = "calibration";
|
||||
nvmem-cells = <&caldata_qca9889>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi {
|
||||
qcom,ath11k-calibration-variant = "Xiaomi-AX3600";
|
||||
};
|
||||
@@ -0,0 +1,311 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
|
||||
|
||||
#include "ipq8074-512m.dtsi"
|
||||
#include "ipq8074-ac-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
led-boot = &led_system_yellow;
|
||||
led-failsafe = &led_system_yellow;
|
||||
led-running = &led_system_blue;
|
||||
led-upgrade = &led_system_yellow;
|
||||
label-mac-device = &dp2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs-append = " root=/dev/ubiblock0_0";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-pins {
|
||||
mdc {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&prng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_nand {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Bootloader will find the NAND DT node by the compatible and
|
||||
* then "fixup" it by adding the partitions from the SMEM table
|
||||
* using the legacy bindings thus making it impossible for us
|
||||
* to change the partition table or utilize NVMEM for calibration.
|
||||
* So add a dummy partitions node that bootloader will populate
|
||||
* and set it as disabled so the kernel ignores it instead of
|
||||
* printing warnings due to the broken way bootloader adds the
|
||||
* partitions.
|
||||
*/
|
||||
partitions {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "0:sbl1";
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "0:mibib";
|
||||
reg = <0x100000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "0:qsee";
|
||||
reg = <0x200000 0x300000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@500000 {
|
||||
label = "0:devcfg";
|
||||
reg = <0x500000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
label = "0:rpm";
|
||||
reg = <0x580000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@600000 {
|
||||
label = "0:cdt";
|
||||
reg = <0x600000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@680000 {
|
||||
label = "0:appsblenv";
|
||||
reg = <0x680000 0x80000>;
|
||||
};
|
||||
|
||||
partition@700000 {
|
||||
label = "0:appsbl";
|
||||
reg = <0x700000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "0:art";
|
||||
reg = <0x800000 0x80000>;
|
||||
read-only;
|
||||
|
||||
compatible = "nvmem-cells";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
macaddr_dp2: macaddr@6 {
|
||||
reg = <0x6 0x6>;
|
||||
};
|
||||
|
||||
macaddr_dp3: macaddr@c {
|
||||
reg = <0xc 0x6>;
|
||||
};
|
||||
|
||||
macaddr_dp4: macaddr@12 {
|
||||
reg = <0x12 0x6>;
|
||||
};
|
||||
|
||||
macaddr_dp5: macaddr@18 {
|
||||
reg = <0x18 0x6>;
|
||||
};
|
||||
|
||||
caldata_qca9889: caldata@4d000 {
|
||||
reg = <0x33000 0x844>;
|
||||
};
|
||||
};
|
||||
|
||||
partition@880000 {
|
||||
label = "bdata";
|
||||
reg = <0x880000 0x80000>;
|
||||
};
|
||||
|
||||
partition@900000 {
|
||||
/* This is crash + crash_syslog parts combined */
|
||||
label = "pstore";
|
||||
reg = <0x900000 0x100000>;
|
||||
};
|
||||
|
||||
/* Make the first rootfs a dedicated ubi partition for kernel */
|
||||
partition@a00000 {
|
||||
label = "ubi_kernel";
|
||||
reg = <0xa00000 0x23c0000>;
|
||||
};
|
||||
|
||||
/* Place the real rootfs in the original second rootfs and
|
||||
* expand it to the end of the nand
|
||||
*/
|
||||
rootfs: partition@2dc0000 {
|
||||
label = "rootfs";
|
||||
reg = <0x2dc0000 0xd240000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
|
||||
|
||||
qca8075_1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
qca8075_2: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
qca8075_3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
qca8075_4: ethernet-phy@4 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
|
||||
switch_lan_bmp = <0x1e>; /* lan port bitmap */
|
||||
switch_wan_bmp = <0x20>; /* wan port bitmap */
|
||||
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
|
||||
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
|
||||
switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
|
||||
bm_tick_mode = <0>; /* bm tick mode */
|
||||
tm_tick_mode = <0>; /* tm tick mode */
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@0 {
|
||||
port_id = <1>;
|
||||
phy_address = <0>;
|
||||
};
|
||||
port@1 {
|
||||
port_id = <2>;
|
||||
phy_address = <1>;
|
||||
};
|
||||
port@2 {
|
||||
port_id = <3>;
|
||||
phy_address = <2>;
|
||||
};
|
||||
port@3 {
|
||||
port_id = <4>;
|
||||
phy_address = <3>;
|
||||
};
|
||||
port@4 {
|
||||
port_id = <5>;
|
||||
phy_address = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp2 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_1>;
|
||||
label = "wan";
|
||||
nvmem-cells = <&macaddr_dp2>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp3 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_2>;
|
||||
label = "lan1";
|
||||
nvmem-cells = <&macaddr_dp3>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp4 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_3>;
|
||||
label = "lan2";
|
||||
nvmem-cells = <&macaddr_dp4>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp5 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_4>;
|
||||
label = "lan3";
|
||||
nvmem-cells = <&macaddr_dp5>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
qcom,ath11k-fw-memory-mode = <1>;
|
||||
};
|
||||
@@ -0,0 +1,46 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/* Copyright (c) 2021, Zhijun You <hujy652@gmail.com> */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8071-ax3600.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Redmi AX6";
|
||||
compatible = "redmi,ax6", "qcom,ipq8074";
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_system_blue: system-blue {
|
||||
label = "blue:system";
|
||||
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_system_yellow: system-yellow {
|
||||
label = "yellow:system";
|
||||
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
network-blue {
|
||||
label = "blue:network";
|
||||
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
network-yellow {
|
||||
label = "yellow:network";
|
||||
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* AX6 can both have NAND of 256MiB or 128MiB.
|
||||
* To be on the safe side, assume 128MiB of NAND.
|
||||
*/
|
||||
&rootfs {
|
||||
reg = <0x2dc0000 0x5220000>;
|
||||
};
|
||||
|
||||
&wifi {
|
||||
qcom,ath11k-calibration-variant = "Redmi-AX6";
|
||||
};
|
||||
@@ -0,0 +1,389 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/* Copyright (c) 2022, Matthew Hagan <mnhagan88@gmail.com> */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8074.dtsi"
|
||||
#include "ipq8074-ac-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Edgecore EAP102";
|
||||
compatible = "edgecore,eap102", "qcom,ipq8074";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
serial1 = &blsp1_uart3;
|
||||
led-boot = &led_system_green;
|
||||
led-failsafe = &led_system_green;
|
||||
led-running = &led_system_green;
|
||||
led-upgrade = &led_system_green;
|
||||
/* Aliases as required by u-boot to patch MAC addresses */
|
||||
ethernet0 = &dp5;
|
||||
ethernet1 = &dp6;
|
||||
label-mac-device = &dp5;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs-append = " root=/dev/ubiblock0_1";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_wanpoe {
|
||||
label = "green:wanpoe";
|
||||
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_wlan2g {
|
||||
label = "green:wlan2g";
|
||||
gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy1radio";
|
||||
};
|
||||
|
||||
led_wlan5g {
|
||||
label = "green:wlan5g";
|
||||
gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy0radio";
|
||||
};
|
||||
|
||||
led_system_green: led_system {
|
||||
label = "green:power";
|
||||
gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-pins {
|
||||
mdc {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
button_pins: button_pins {
|
||||
reset_button {
|
||||
pins = "gpio66";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "0:sbl1";
|
||||
reg = <0x0 0x50000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@50000 {
|
||||
label = "0:mibib";
|
||||
reg = <0x50000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "0:bootconfig";
|
||||
reg = <0x60000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "0:bootconfig1";
|
||||
reg = <0x80000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@a0000 {
|
||||
label = "0:qsee";
|
||||
reg = <0xa0000 0x180000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@220000 {
|
||||
label = "0:qsee_1";
|
||||
reg = <0x220000 0x180000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3a0000 {
|
||||
label = "0:devcfg";
|
||||
reg = <0x3a0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3b0000 {
|
||||
label = "0:devcfg_1";
|
||||
reg = <0x3b0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3c0000 {
|
||||
label = "0:apdp";
|
||||
reg = <0x3c0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3d0000 {
|
||||
label = "0:apdp_1";
|
||||
reg = <0x3d0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3e0000 {
|
||||
label = "0:rpm";
|
||||
reg = <0x3e0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@420000 {
|
||||
label = "0:rpm_1";
|
||||
reg = <0x420000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@460000 {
|
||||
label = "0:cdt";
|
||||
reg = <0x460000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@470000 {
|
||||
label = "0:cdt_1";
|
||||
reg = <0x470000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@480000 {
|
||||
label = "0:appsblenv";
|
||||
reg = <0x480000 0x10000>;
|
||||
};
|
||||
|
||||
partition@490000 {
|
||||
label = "0:appsbl";
|
||||
reg = <0x490000 0xc0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@550000 {
|
||||
label = "0:appsbl_1";
|
||||
reg = <0x530000 0xc0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@610000 {
|
||||
label = "0:art";
|
||||
reg = <0x610000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@650000 {
|
||||
label = "0:ethphyfw";
|
||||
reg = <0x650000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@6d0000 {
|
||||
label = "0:product_info";
|
||||
reg = <0x6d0000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@750000 {
|
||||
label = "priv_data1";
|
||||
reg = <0x750000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@760000 {
|
||||
label = "priv_data2";
|
||||
reg = <0x760000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&prng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qusb_phy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssphy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <8>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "rootfs1";
|
||||
reg = <0x0000000 0x3400000>;
|
||||
};
|
||||
|
||||
partition@3400000 {
|
||||
label = "0:wififw";
|
||||
reg = <0x3400000 0x800000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3c00000 {
|
||||
label = "rootfs2";
|
||||
reg = <0x3c00000 0x3400000>;
|
||||
};
|
||||
|
||||
partition@7000000 {
|
||||
label = "0:wififw_1";
|
||||
reg = <0x7000000 0x800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
qca8081_24: ethernet-phy@24 {
|
||||
compatible = "ethernet-phy-id004d.d101";
|
||||
reg = <24>;
|
||||
reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
qca8081_28: ethernet-phy@28 {
|
||||
compatible = "ethernet-phy-id004d.d101";
|
||||
reg = <28>;
|
||||
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
|
||||
switch_lan_bmp = <0x3e>; /* lan port bitmap */
|
||||
switch_wan_bmp = <0x40>; /* wan port bitmap */
|
||||
switch_mac_mode = <0xff>; /* mac mode for uniphy instance0*/
|
||||
switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
|
||||
switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/
|
||||
bm_tick_mode = <0>; /* bm tick mode */
|
||||
tm_tick_mode = <0>; /* tm tick mode */
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@4 {
|
||||
port_id = <5>;
|
||||
phy_address = <24>;
|
||||
port_mac_sel = "QGMAC_PORT";
|
||||
};
|
||||
port@5 {
|
||||
port_id = <6>;
|
||||
phy_address = <28>;
|
||||
port_mac_sel = "QGMAC_PORT";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp5 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8081_28>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
&dp6 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8081_24>;
|
||||
label = "lan";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
qcom,ath11k-calibration-variant = "Edgecore-EAP102";
|
||||
};
|
||||
@@ -0,0 +1,410 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/* Copyright (c) 2021, Dirk Buchwalder <buchwalder@posteo.de> */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8074.dtsi"
|
||||
#include "ipq8074-hk-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
model = "QNAP 301w";
|
||||
compatible = "qnap,301w", "qcom,ipq8074";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
/*
|
||||
* Aliases as required by u-boot
|
||||
* to patch MAC addresses
|
||||
*/
|
||||
led-boot = &led_system_red;
|
||||
led-failsafe = &led_system_red;
|
||||
led-running = &led_pwr_green;
|
||||
led-upgrade = &led_system_red;
|
||||
ethernet0 = &dp1;
|
||||
ethernet1 = &dp2;
|
||||
ethernet2 = &dp3;
|
||||
ethernet3 = &dp4;
|
||||
ethernet4 = &dp5;
|
||||
ethernet5 = &dp6_syn;
|
||||
label-mac-device = &dp1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wps-button {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
reset-button {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&leds_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
led_system_green: led-system-green {
|
||||
label = "green:system";
|
||||
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led_system_red: led-system-red {
|
||||
label = "red:system";
|
||||
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led_pwr_green: led-pwr-green {
|
||||
label = "green:pwr";
|
||||
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led-wifi-green {
|
||||
label = "green:wifi";
|
||||
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led-lan4-green {
|
||||
label = "green:lan4";
|
||||
gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led-lan4-amber {
|
||||
label = "amber:lan4";
|
||||
gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
};
|
||||
|
||||
led-lan3-green {
|
||||
label = "green:lan3";
|
||||
gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led-lan3-amber {
|
||||
label = "amber:lan3";
|
||||
gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
};
|
||||
|
||||
led-lan2-green {
|
||||
label = "green:lan2";
|
||||
gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led-lan2-amber {
|
||||
label = "amber:lan2";
|
||||
gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
};
|
||||
|
||||
led-lan1-green {
|
||||
label = "green:lan1";
|
||||
gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led-lan1-amber {
|
||||
label = "amber:lan1";
|
||||
gpios = <&tlmm 15 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
};
|
||||
|
||||
led-10g-1-green {
|
||||
label = "green:10g_1";
|
||||
gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led-10g-1-amber {
|
||||
label = "amber:10g_1";
|
||||
gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
};
|
||||
|
||||
led-10g-2-green {
|
||||
label = "green:10g_2";
|
||||
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led-10g-2-amber {
|
||||
label = "amber:10g_2";
|
||||
gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
|
||||
mdio_pins: mdio-state {
|
||||
mdc-pins {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio-pins {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
button_pins: button-state {
|
||||
wps-pins {
|
||||
pins = "gpio57";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
rst-pins {
|
||||
pins = "gpio67";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
leds_pins: leds-state {
|
||||
pins = "gpio1", "gpio3", "gpio4", "gpio6", "gpio7", "gpio8",
|
||||
"gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio42",
|
||||
"gpio51", "gpio52", "gpio54", "gpio56";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&prng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssphy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qusb_phy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssphy_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qusb_phy_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 { /* BLSP1 QUP1 */
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "qcom,smem-part";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
|
||||
|
||||
aqr113c_0: ethernet-phy@0 {
|
||||
compatible ="ethernet-phy-ieee802.3-c45";
|
||||
reg = <0>;
|
||||
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
aqr113c_8: ethernet-phy@8 {
|
||||
compatible ="ethernet-phy-ieee802.3-c45";
|
||||
reg = <8>;
|
||||
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
qca8075_16: ethernet-phy@16 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <16>;
|
||||
};
|
||||
|
||||
qca8075_17: ethernet-phy@17 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
qca8075_18: ethernet-phy@18 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
qca8075_19: ethernet-phy@19 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <19>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
/* According to the stock dts from the QNAP gpl drop
|
||||
* the emmc has a problem with the hs400 > hs200 speed switch.
|
||||
* Therefore remove the mmc-hs400-1_8v property
|
||||
*/
|
||||
/delete-property/ mmc-hs400-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-ddr-1_8v;
|
||||
vqmmc-supply = <&l11>;
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
|
||||
switch_lan_bmp = <0x3e>; /* lan port bitmap */
|
||||
switch_wan_bmp = <0xc0>; /* wan port bitmap */
|
||||
switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
|
||||
switch_mac_mode1 = <0xd>; /* mac mode for uniphy instance1*/
|
||||
switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
|
||||
bm_tick_mode = <0>; /* bm tick mode */
|
||||
tm_tick_mode = <0>; /* tm tick mode */
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@0 {
|
||||
port_id = <1>;
|
||||
phy_address = <16>;
|
||||
};
|
||||
port@1 {
|
||||
port_id = <2>;
|
||||
phy_address = <17>;
|
||||
};
|
||||
port@2 {
|
||||
port_id = <3>;
|
||||
phy_address = <18>;
|
||||
};
|
||||
port@3 {
|
||||
port_id = <4>;
|
||||
phy_address = <19>;
|
||||
};
|
||||
port@4 {
|
||||
port_id = <5>;
|
||||
phy_address = <8>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
ethernet-phy-ieee802.3-c45;
|
||||
};
|
||||
port@5 {
|
||||
port_id = <6>;
|
||||
phy_address = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
ethernet-phy-ieee802.3-c45;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp1 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_16>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
&dp2 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_17>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
&dp3 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_18>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
&dp4 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_19>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
&dp5 {
|
||||
status = "okay";
|
||||
qcom,mactype = <1>;
|
||||
phy-handle = <&aqr113c_8>;
|
||||
label = "10g-1";
|
||||
};
|
||||
|
||||
&dp6_syn {
|
||||
status = "okay";
|
||||
phy-handle = <&aqr113c_0>;
|
||||
label = "10g-2";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
qcom,ath11k-calibration-variant = "QNAP-301w";
|
||||
};
|
||||
@@ -0,0 +1,522 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8074.dtsi"
|
||||
#include "ipq8074-hk-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
model = "Xiaomi AX9000";
|
||||
compatible = "xiaomi,ax9000", "qcom,ipq8074";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
led-boot = &led_system_yellow;
|
||||
led-failsafe = &led_system_yellow;
|
||||
led-running = &led_system_blue;
|
||||
led-upgrade = &led_system_yellow;
|
||||
label-mac-device = &dp5;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs-append = " root=/dev/ubiblock0_0";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps"; /* Labeled Mesh on the device */
|
||||
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_system_blue: system-blue {
|
||||
label = "blue:system";
|
||||
gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
|
||||
led_system_yellow: system-yellow {
|
||||
label = "yellow:system";
|
||||
gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
};
|
||||
|
||||
network-yellow {
|
||||
label = "yellow:network";
|
||||
gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
};
|
||||
|
||||
network-blue {
|
||||
label = "blue:network";
|
||||
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
|
||||
top-red {
|
||||
label = "red:top";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
top-green {
|
||||
label = "green:top";
|
||||
gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
top-blue {
|
||||
label = "blue:top";
|
||||
gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-pins {
|
||||
mdc {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c_pins: i2c-pins {
|
||||
pins = "gpio0", "gpio2";
|
||||
function = "blsp5_i2c";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_i2c6 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&i2c_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&prng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_nand {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Bootloader will find the NAND DT node by the compatible and
|
||||
* then "fixup" it by adding the partitions from the SMEM table
|
||||
* using the legacy bindings thus making it impossible for us
|
||||
* to change the partition table or utilize NVMEM for calibration.
|
||||
* So add a dummy partitions node that bootloader will populate
|
||||
* and set it as disabled so the kernel ignores it instead of
|
||||
* printing warnings due to the broken way bootloader adds the
|
||||
* partitions.
|
||||
*/
|
||||
partitions {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "0:sbl1";
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "0:mibib";
|
||||
reg = <0x100000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "0:bootconfig";
|
||||
reg = <0x200000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "0:bootconfig1";
|
||||
reg = <0x280000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@300000 {
|
||||
label = "0:qsee";
|
||||
reg = <0x300000 0x300000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@600000 {
|
||||
label = "0:qsee_1";
|
||||
reg = <0x600000 0x300000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@900000 {
|
||||
label = "0:devcfg";
|
||||
reg = <0x900000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@980000 {
|
||||
label = "0:devcfg_1";
|
||||
reg = <0x980000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@a00000 {
|
||||
label = "0:apdp";
|
||||
reg = <0xa00000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@a80000 {
|
||||
label = "0:apdp_1";
|
||||
reg = <0xa80000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@b00000 {
|
||||
label = "0:rpm";
|
||||
reg = <0xb00000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@b80000 {
|
||||
label = "0:rpm_1";
|
||||
reg = <0xb80000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c00000 {
|
||||
label = "0:cdt";
|
||||
reg = <0xc00000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c80000 {
|
||||
label = "0:cdt_1";
|
||||
reg = <0xc80000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@d00000 {
|
||||
label = "0:appsblenv";
|
||||
reg = <0xd00000 0x80000>;
|
||||
};
|
||||
|
||||
partition@d80000 {
|
||||
label = "0:appsbl";
|
||||
reg = <0xd80000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@e80000 {
|
||||
label = "0:appsbl_1";
|
||||
reg = <0xe80000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@f80000 {
|
||||
label = "0:art";
|
||||
reg = <0xf80000 0x80000>;
|
||||
read-only;
|
||||
|
||||
compatible = "nvmem-cells";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
macaddr_dp1: macaddr@0 {
|
||||
reg = <0x0 0x6>;
|
||||
};
|
||||
|
||||
macaddr_dp2: macaddr@6 {
|
||||
reg = <0x6 0x6>;
|
||||
};
|
||||
|
||||
macaddr_dp3: macaddr@c {
|
||||
reg = <0xc 0x6>;
|
||||
};
|
||||
|
||||
macaddr_dp4: macaddr@12 {
|
||||
reg = <0x12 0x6>;
|
||||
};
|
||||
|
||||
macaddr_dp5: macaddr@18 {
|
||||
reg = <0x18 0x6>;
|
||||
};
|
||||
|
||||
caldata_qca9889: caldata@4d000 {
|
||||
reg = <0x4d000 0x844>;
|
||||
};
|
||||
};
|
||||
|
||||
partition@1000000 {
|
||||
label = "bdata";
|
||||
reg = <0x1000000 0x80000>;
|
||||
};
|
||||
|
||||
partition@1080000 {
|
||||
/* This is crash + crash_syslog parts combined */
|
||||
label = "pstore";
|
||||
reg = <0x1080000 0x100000>;
|
||||
};
|
||||
|
||||
partition@1180000 {
|
||||
label = "ubi_kernel";
|
||||
reg = <0x1180000 0x3800000>;
|
||||
};
|
||||
|
||||
partition@4980000 {
|
||||
label = "rootfs";
|
||||
reg = <0x4980000 0xb680000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qusb_phy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssphy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
|
||||
|
||||
qca8075_0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
qca8075_1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
qca8075_2: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
qca8075_3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
qca8081: ethernet-phy@24 {
|
||||
compatible = "ethernet-phy-id004d.d101";
|
||||
reg = <24>;
|
||||
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
|
||||
switch_lan_bmp = <0x1e>; /* lan port bitmap */
|
||||
switch_wan_bmp = <0x20>; /* wan port bitmap */
|
||||
switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
|
||||
switch_mac_mode1 = <0xc>; /* mac mode for uniphy instance1*/
|
||||
switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
|
||||
bm_tick_mode = <0>; /* bm tick mode */
|
||||
tm_tick_mode = <0>; /* tm tick mode */
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@0 {
|
||||
port_id = <1>;
|
||||
phy_address = <0>;
|
||||
};
|
||||
port@1 {
|
||||
port_id = <2>;
|
||||
phy_address = <1>;
|
||||
};
|
||||
port@2 {
|
||||
port_id = <3>;
|
||||
phy_address = <2>;
|
||||
};
|
||||
port@3 {
|
||||
port_id = <4>;
|
||||
phy_address = <3>;
|
||||
};
|
||||
port@4 {
|
||||
port_id = <5>;
|
||||
phy_address = <24>;
|
||||
port_mac_sel = "QGMAC_PORT";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp1 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_0>;
|
||||
label = "lan4";
|
||||
nvmem-cells = <&macaddr_dp1>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp2 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_1>;
|
||||
label = "lan3";
|
||||
nvmem-cells = <&macaddr_dp2>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp3 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_2>;
|
||||
label = "lan2";
|
||||
nvmem-cells = <&macaddr_dp3>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp4 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_3>;
|
||||
label = "lan1";
|
||||
nvmem-cells = <&macaddr_dp4>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp5 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8081>;
|
||||
label = "wan";
|
||||
nvmem-cells = <&macaddr_dp5>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&pcie_qmp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
|
||||
perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
wifi@1,0 {
|
||||
status = "okay";
|
||||
|
||||
/* ath11k has no DT compatible for PCI cards */
|
||||
compatible = "pci17cb,1104";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
|
||||
qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_qmp1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
|
||||
perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
bridge@1,0 {
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
wifi@1,0 {
|
||||
status = "okay";
|
||||
|
||||
compatible = "qcom,ath10k";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
|
||||
qcom,ath10k-calibration-variant = "Xiaomi-AX9000";
|
||||
nvmem-cell-names = "calibration";
|
||||
nvmem-cells = <&caldata_qca9889>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
|
||||
};
|
||||
@@ -0,0 +1,243 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/* Copyright (c) 2022, Robert Marko <robimarko@gmail.com> */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8074.dtsi"
|
||||
#include "ipq8074-hk-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
model = "Dynalink DL-WRX36";
|
||||
compatible = "dynalink,dl-wrx36", "qcom,ipq8074";
|
||||
|
||||
aliases {
|
||||
led-boot = &led_system_red;
|
||||
led-failsafe = &led_system_red;
|
||||
led-running = &led_system_blue;
|
||||
led-upgrade = &led_system_red;
|
||||
serial0 = &blsp1_uart5;
|
||||
/* Aliases as required by u-boot to patch MAC addresses */
|
||||
ethernet0 = &dp6_syn;
|
||||
ethernet1 = &dp4;
|
||||
ethernet2 = &dp3;
|
||||
ethernet3 = &dp2;
|
||||
ethernet4 = &dp1;
|
||||
label-mac-device = &dp6_syn;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs-append = " root=/dev/ubiblock0_1";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_system_blue: system-blue {
|
||||
label = "blue:system";
|
||||
gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
|
||||
led_system_red: system-red {
|
||||
label = "red:system";
|
||||
gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-pins {
|
||||
mdc {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&prng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <8>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
partitions {
|
||||
compatible = "qcom,smem-part";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qusb_phy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssphy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
|
||||
|
||||
qca8075_0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
qca8075_1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
qca8075_2: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
qca8075_3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
qca8081: ethernet-phy@28 {
|
||||
compatible = "ethernet-phy-id004d.d101";
|
||||
reg = <28>;
|
||||
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
|
||||
switch_lan_bmp = <0x3e>; /* lan port bitmap */
|
||||
switch_wan_bmp = <0x40>; /* wan port bitmap */
|
||||
switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
|
||||
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
|
||||
switch_mac_mode2 = <0xc>; /* mac mode for uniphy instance2*/
|
||||
bm_tick_mode = <0>; /* bm tick mode */
|
||||
tm_tick_mode = <0>; /* tm tick mode */
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@0 {
|
||||
port_id = <1>;
|
||||
phy_address = <0>;
|
||||
};
|
||||
port@1 {
|
||||
port_id = <2>;
|
||||
phy_address = <1>;
|
||||
};
|
||||
port@2 {
|
||||
port_id = <3>;
|
||||
phy_address = <2>;
|
||||
};
|
||||
port@3 {
|
||||
port_id = <4>;
|
||||
phy_address = <3>;
|
||||
};
|
||||
port@5 {
|
||||
port_id = <6>;
|
||||
phy_address = <28>;
|
||||
port_mac_sel = "QGMAC_PORT";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp1 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
&dp2 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
&dp3 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
&dp4 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
&dp6_syn {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8081>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
qcom,ath11k-calibration-variant = "Dynalink-DL-WRX36";
|
||||
};
|
||||
@@ -0,0 +1,308 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8074.dtsi"
|
||||
#include "ipq8074-hk-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
model = "prpl Foundation Haze";
|
||||
compatible = "prpl,haze", "qcom,ipq8074";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
/* Aliases are required by U-Boot to patch MAC addresses */
|
||||
ethernet0 = &dp6_syn;
|
||||
ethernet1 = &dp4;
|
||||
ethernet2 = &dp3;
|
||||
ethernet3 = &dp2;
|
||||
label-mac-device = &dp6_syn;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wps-button {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
reset-button {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-state {
|
||||
mdc-pins {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio-pins {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
button_pins: button-state {
|
||||
wps-pins {
|
||||
pins = "gpio42";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
rst-pins {
|
||||
pins = "gpio44";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&prng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssphy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qusb_phy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssphy_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qusb_phy_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 { /* BLSP1 QUP1 */
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "qcom,smem-part";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
|
||||
|
||||
qca8075_1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
qca8075_2: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
qca8075_3: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
qca8075_4: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
aqr113c: ethernet-phy@5 {
|
||||
compatible ="ethernet-phy-ieee802.3-c45";
|
||||
reg = <8>;
|
||||
reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
vqmmc-supply = <&l11>;
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
|
||||
switch_lan_bmp = <0x1e>; /* lan port bitmap */
|
||||
switch_wan_bmp = <0x60>; /* wan port bitmap */
|
||||
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
|
||||
switch_mac_mode1 = <0xe>; /* mac mode for uniphy instance1*/
|
||||
switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
|
||||
bm_tick_mode = <0>; /* bm tick mode */
|
||||
tm_tick_mode = <0>; /* tm tick mode */
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@0 {
|
||||
port_id = <1>;
|
||||
phy_address = <0>;
|
||||
};
|
||||
port@1 {
|
||||
port_id = <2>;
|
||||
phy_address = <1>;
|
||||
};
|
||||
port@2 {
|
||||
port_id = <3>;
|
||||
phy_address = <2>;
|
||||
};
|
||||
port@3 {
|
||||
port_id = <4>;
|
||||
phy_address = <3>;
|
||||
};
|
||||
port@4 {
|
||||
port_id = <6>;
|
||||
phy_address = <8>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
ethernet-phy-ieee802.3-c45;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Dummy LAN port */
|
||||
&dp1 {
|
||||
status = "disabled";
|
||||
phy-handle = <&qca8075_1>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
&dp2 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
&dp3 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_3>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
&dp4 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_4>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
&dp6_syn {
|
||||
status = "okay";
|
||||
qcom,mactype = <1>;
|
||||
phy-handle = <&aqr113c>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
&pcie_qmp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
|
||||
perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00020000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_qmp1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
|
||||
perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
|
||||
|
||||
bridge@1,0 {
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
wifi@1,0 {
|
||||
status = "okay";
|
||||
|
||||
/* ath11k has no DT compatible for PCI cards */
|
||||
compatible = "pci17cb,1104";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
|
||||
qcom,ath11k-calibration-variant = "prpl-Haze";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
qcom,ath11k-calibration-variant = "prpl-Haze";
|
||||
};
|
||||
@@ -0,0 +1,191 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8074.dtsi"
|
||||
#include "ipq8074-hk-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Netgear WAX218";
|
||||
compatible = "netgear,wax218", "qcom,ipq8074";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
led-boot = &led_power_amber;
|
||||
led-failsafe = &led_power_amber;
|
||||
led-running = &led_power_amber;
|
||||
led-upgrade = &led_power_amber;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
/*
|
||||
* Netgear's U-Boot adds "ubi.mtd=rootfs root=mtd:ubi_rootfs"
|
||||
* That fails to create a UBI block device, so add it here.
|
||||
*/
|
||||
bootargs-append = " ubi.block=0,rootfs root=/dev/ubiblock0_1";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
led_spi {
|
||||
compatible = "spi-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sck-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
|
||||
mosi-gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
led_gpio: led_gpio@0 {
|
||||
compatible = "fairchild,74hc595";
|
||||
reg = <0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
registers-number = <1>;
|
||||
enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_power_amber: led_power {
|
||||
label = "amber:power";
|
||||
gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_lan {
|
||||
label = "blue:lan";
|
||||
gpios = <&led_gpio 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_wlan_2g {
|
||||
label = "blue:wlan2g";
|
||||
gpios = <&led_gpio 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_wlan_5g {
|
||||
label = "blue:wlan5g";
|
||||
gpios = <&led_gpio 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>;
|
||||
switch_lan_bmp = <0x3e>;
|
||||
switch_wan_bmp = <0x40>;
|
||||
switch_mac_mode = <0x00>;
|
||||
switch_mac_mode1 = <0xff>;
|
||||
switch_mac_mode2 = <0x0f>;
|
||||
bm_tick_mode = <0>;
|
||||
tm_tick_mode = <0>;
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@5 {
|
||||
port_id = <6>;
|
||||
phy_address = <28>;
|
||||
port_mac_sel = "QGMAC_PORT";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-pins {
|
||||
mdc {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
|
||||
|
||||
qca8081_28: ethernet-phy@28 {
|
||||
reg = <28>;
|
||||
};
|
||||
};
|
||||
|
||||
&dp6_syn {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8081_28>;
|
||||
label = "lan";
|
||||
nvmem-cells = <&macaddr_ubootenv_ethaddr>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
partitions {
|
||||
compatible = "qcom,smem-part";
|
||||
|
||||
partition-0-appsblenv {
|
||||
compatible = "fixed-partitions";
|
||||
label = "0:appsblenv";
|
||||
read-only;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
compatible = "u-boot,env";
|
||||
label = "env-data";
|
||||
reg = <0x0 0x40000>;
|
||||
|
||||
macaddr_ubootenv_ethaddr: ethaddr {};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
qcom,ath11k-calibration-variant = "Netgear-WAX218";
|
||||
};
|
||||
@@ -0,0 +1,487 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/* Copyright 2023 Nokia */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8074.dtsi"
|
||||
#include "ipq8074-hk-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
model = "Compex WPQ873";
|
||||
compatible = "compex,wpq873", "qcom,ipq8074";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
led-boot = &led_power_blue;
|
||||
led-failsafe = &led_power_red;
|
||||
led-running = &led_system_green;
|
||||
led-upgrade = &led_system_blue;
|
||||
/* Aliases as required by u-boot to patch MAC addresses */
|
||||
ethernet0 = &dp6;
|
||||
ethernet1 = &dp2;
|
||||
ethernet2 = &dp3;
|
||||
ethernet3 = &dp4;
|
||||
label-mac-device = &dp6;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs-append = " root=/dev/ubiblock0_1";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_power_red: power-red {
|
||||
label = "red:power";
|
||||
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led_power_blue: power-blue {
|
||||
label = "blue:power";
|
||||
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
|
||||
led_system_red: system-red {
|
||||
label = "red:system";
|
||||
gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led_system_green: system-green {
|
||||
label = "green:system";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led_system_blue: system-blue {
|
||||
label = "blue:system";
|
||||
gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-pins {
|
||||
mdc {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c_pins: i2c-pins {
|
||||
pins = "gpio0", "gpio2";
|
||||
function = "blsp5_i2c";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_i2c6 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&i2c_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&prng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-pins {
|
||||
mdc {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
button_pins: button_pins {
|
||||
reset_button {
|
||||
pins = "gpio66";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_spi1 {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "0:sbl1";
|
||||
reg = <0x0 0x50000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@50000 {
|
||||
label = "0:mibib";
|
||||
reg = <0x50000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "0:bootconfig";
|
||||
reg = <0x60000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "0:bootconfig1";
|
||||
reg = <0x80000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@a0000 {
|
||||
label = "0:qsee";
|
||||
reg = <0xa0000 0x180000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@220000 {
|
||||
label = "0:qsee_1";
|
||||
reg = <0x220000 0x180000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3a0000 {
|
||||
label = "0:devcfg";
|
||||
reg = <0x3a0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3b0000 {
|
||||
label = "0:devcfg_1";
|
||||
reg = <0x3b0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3c0000 {
|
||||
label = "0:apdp";
|
||||
reg = <0x3c0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3d0000 {
|
||||
label = "0:apdp_1";
|
||||
reg = <0x3d0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3e0000 {
|
||||
label = "0:rpm";
|
||||
reg = <0x3e0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@420000 {
|
||||
label = "0:rpm_1";
|
||||
reg = <0x420000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@460000 {
|
||||
label = "0:cdt";
|
||||
reg = <0x460000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@470000 {
|
||||
label = "0:cdt_1";
|
||||
reg = <0x470000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@480000 {
|
||||
label = "0:appsblenv";
|
||||
reg = <0x480000 0x10000>;
|
||||
};
|
||||
|
||||
partition@490000 {
|
||||
label = "0:appsbl";
|
||||
reg = <0x490000 0xa0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@550000 {
|
||||
label = "0:appsbl_1";
|
||||
reg = <0x530000 0xa0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@610000 {
|
||||
label = "0:art";
|
||||
reg = <0x5d0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@650000 {
|
||||
label = "0:ethphyfw";
|
||||
reg = <0x610000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qpic_nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <8>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "rootfs";
|
||||
reg = <0x0000000 0x3400000>;
|
||||
};
|
||||
|
||||
partition@3400000 {
|
||||
label = "0:wififw";
|
||||
reg = <0x3400000 0x800000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3c00000 {
|
||||
label = "rootfs_1";
|
||||
reg = <0x3c00000 0x3400000>;
|
||||
};
|
||||
|
||||
partition@7000000 {
|
||||
label = "0:wififw_1";
|
||||
reg = <0x7000000 0x800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qusb_phy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qusb_phy_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssphy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssphy_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
|
||||
|
||||
qca8075_1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
qca8075_2: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
qca8075_3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
qca8081: ethernet-phy@28 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <28>;
|
||||
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
|
||||
switch_lan_bmp = <0x3e>; /* lan port bitmap */
|
||||
switch_wan_bmp = <0x40>; /* wan port bitmap */
|
||||
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
|
||||
switch_mac_mode1 = <0x0f>; /* mac mode for uniphy instance1*/
|
||||
switch_mac_mode2 = <0x0f>; /* mac mode for uniphy instance2*/
|
||||
bm_tick_mode = <0>; /* bm tick mode */
|
||||
tm_tick_mode = <0>; /* tm tick mode */
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@2 {
|
||||
port_id = <2>;
|
||||
phy_address = <1>;
|
||||
};
|
||||
port@3 {
|
||||
port_id = <3>;
|
||||
phy_address = <2>;
|
||||
};
|
||||
port@4 {
|
||||
port_id = <4>;
|
||||
phy_address = <3>;
|
||||
};
|
||||
port@5 {
|
||||
port_id = <6>;
|
||||
phy_address = <28>;
|
||||
port_mac_sel = "QGMAC_PORT";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp2 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
&dp3 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
&dp4 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
&dp6 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8081>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
&pcie_qmp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
|
||||
perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
|
||||
|
||||
bridge@0,0 {
|
||||
reg = <0x00020000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_qmp1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
|
||||
perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
bridge@1,0 {
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
qcom,ath11k-calibration-variant = "Compex-WPQ873";
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include "ipq8074.dtsi"
|
||||
|
||||
&tzapp_region {
|
||||
reg = <0x0 0x4a400000 0x0 0x100000>;
|
||||
};
|
||||
|
||||
&q6_region {
|
||||
reg = <0x0 0x4b000000 0x0 0x3700000>;
|
||||
};
|
||||
|
||||
&q6_etr_region {
|
||||
reg = <0x0 0x4e700000 0x0 0x100000>;
|
||||
};
|
||||
|
||||
&m3_dump_region {
|
||||
reg = <0x0 0x4e800000 0x0 0x100000>;
|
||||
};
|
||||
@@ -0,0 +1,123 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include "ipq8074-cpr-regulator.dtsi"
|
||||
|
||||
&CPU0 {
|
||||
cpu-supply = <&apc_vreg>;
|
||||
voltage-tolerance = <1>;
|
||||
};
|
||||
|
||||
&CPU1 {
|
||||
cpu-supply = <&apc_vreg>;
|
||||
voltage-tolerance = <1>;
|
||||
};
|
||||
|
||||
&CPU2 {
|
||||
cpu-supply = <&apc_vreg>;
|
||||
voltage-tolerance = <1>;
|
||||
};
|
||||
|
||||
&CPU3 {
|
||||
cpu-supply = <&apc_vreg>;
|
||||
voltage-tolerance = <1>;
|
||||
};
|
||||
&cpu0_thermal {
|
||||
trips {
|
||||
cpu0_passive: cpu-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu0_passive>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu1_thermal {
|
||||
trips {
|
||||
cpu1_passive: cpu-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu1_passive>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu2_thermal {
|
||||
trips {
|
||||
cpu2_passive: cpu-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu2_passive>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu3_thermal {
|
||||
trips {
|
||||
cpu3_passive: cpu-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu3_passive>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cluster_thermal {
|
||||
trips {
|
||||
cluster_passive: cluster-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cluster_passive>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,228 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include "pmp8074.dtsi"
|
||||
|
||||
&soc {
|
||||
apc_apm: apm@b111000 {
|
||||
compatible = "qcom,ipq807x-apm";
|
||||
reg = <0xb111000 0x1000>;
|
||||
reg-names = "pm-apcc-glb";
|
||||
qcom,apm-post-halt-delay = <0x2>;
|
||||
qcom,apm-halt-clk-delay = <0x11>;
|
||||
qcom,apm-resume-clk-delay = <0x10>;
|
||||
qcom,apm-sel-switch-delay = <0x01>;
|
||||
};
|
||||
|
||||
apc_cpr: cpr4-ctrl@b018000 {
|
||||
compatible = "qcom,cpr4-ipq807x-apss-regulator";
|
||||
reg = <0xb018000 0x4000>, <0xa4000 0x1000>, <0x0193d008 0x4>;
|
||||
reg-names = "cpr_ctrl", "fuse_base", "cpr_tcsr_reg";
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "cpr";
|
||||
qcom,cpr-ctrl-name = "apc";
|
||||
qcom,cpr-sensor-time = <1000>;
|
||||
qcom,cpr-loop-time = <5000000>;
|
||||
qcom,cpr-idle-cycles = <15>;
|
||||
qcom,cpr-step-quot-init-min = <12>;
|
||||
qcom,cpr-step-quot-init-max = <14>;
|
||||
qcom,cpr-count-mode = <0>; /* All-at-once */
|
||||
qcom,cpr-count-repeat = <14>;
|
||||
qcom,cpr-down-error-step-limit = <1>;
|
||||
qcom,cpr-up-error-step-limit = <1>;
|
||||
qcom,apm-ctrl = <&apc_apm>;
|
||||
qcom,apm-threshold-voltage = <848000>;
|
||||
vdd-supply = <&s3>;
|
||||
qcom,voltage-step = <8000>;
|
||||
|
||||
thread@0 {
|
||||
qcom,cpr-thread-id = <0>;
|
||||
qcom,cpr-consecutive-up = <0>;
|
||||
qcom,cpr-consecutive-down = <0>;
|
||||
qcom,cpr-up-threshold = <4>;
|
||||
qcom,cpr-down-threshold = <1>;
|
||||
|
||||
apc_vreg: regulator {
|
||||
regulator-name = "apc_corner";
|
||||
regulator-min-microvolt = <1>;
|
||||
regulator-max-microvolt = <6>;
|
||||
qcom,cpr-part-types = <2>;
|
||||
qcom,cpr-parts-voltage = <1048000>;
|
||||
qcom,cpr-parts-voltage-v2 = <992000>;
|
||||
qcom,cpr-fuse-corners = <4>;
|
||||
qcom,cpr-fuse-combos = <8>;
|
||||
qcom,cpr-corners = <6>;
|
||||
qcom,cpr-speed-bins = <1>;
|
||||
qcom,cpr-speed-bin-corners = <6>;
|
||||
qcom,cpr-corner-fmax-map = <1 3 5 6>;
|
||||
qcom,allow-voltage-interpolation;
|
||||
qcom,allow-quotient-interpolation;
|
||||
qcom,cpr-scaled-open-loop-voltage-as-ceiling;
|
||||
qcom,cpr-voltage-ceiling =
|
||||
<840000 904000 944000
|
||||
984000 992000 1064000>;
|
||||
qcom,cpr-voltage-floor =
|
||||
<592000 648000 712000
|
||||
744000 784000 848000>;
|
||||
qcom,corner-frequencies =
|
||||
<1017600000 1382400000 1651200000
|
||||
1843200000 1920000000 2208000000>;
|
||||
|
||||
/* TT/FF parts i.e. turbo L1 OL voltage < 1048 mV */
|
||||
qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
|
||||
/* Speed bin 0; CPR rev 0..7 */
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 12000>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>;
|
||||
|
||||
/* SS parts i.e turbo L1 OL voltage >= 1048 mV */
|
||||
qcom,cpr-open-loop-voltage-fuse-adjustment-1 =
|
||||
/* Speed bin 0; CPR rev 0..7 */
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 20000 26000 0 20000>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>;
|
||||
|
||||
/* v2 - FF parts i.e. turbo L1 OL voltage < 992 mV */
|
||||
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0 =
|
||||
/* Speed bin 0; CPR rev 0..7 */
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>;
|
||||
|
||||
/* v2 - SS/TT parts i.e turbo L1 OL voltage >= 992 mV */
|
||||
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1 =
|
||||
/* Speed bin 0; CPR rev 0..7 */
|
||||
< 0 0 0 0>,
|
||||
< 0 7000 36000 4000>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>;
|
||||
|
||||
/* v2 - FF parts i.e. turbo L1 OL voltage < 992 mV */
|
||||
qcom,cpr-closed-loop-voltage-adjustment-v2-0 =
|
||||
/* Speed bin 0; CPR rev 0..7 */
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>;
|
||||
|
||||
/* v2 - SS/TT parts i.e turbo L1 OL voltage >= 992 mV */
|
||||
qcom,cpr-closed-loop-voltage-adjustment-v2-1 =
|
||||
/* Speed bin 0; CPR rev 0..7 */
|
||||
< 0 0 0 0>,
|
||||
< 0 0 19000 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>,
|
||||
< 0 0 0 0>;
|
||||
|
||||
qcom,cpr-ro-scaling-factor =
|
||||
< 3970 4150 0 2280 2520 2470 2250 2280
|
||||
2390 2330 2530 2500 850 2900 2510 2170 >,
|
||||
< 3970 4150 0 2280 2520 2470 2250 2280
|
||||
2390 2330 2530 2500 850 2900 2510 2170 >,
|
||||
< 3970 4150 0 2280 2520 2470 2250 2280
|
||||
2390 2330 2530 2500 850 2900 2510 2170 >,
|
||||
< 3970 4150 0 2280 2520 2470 2250 2280
|
||||
2390 2330 2530 2500 850 2900 2510 2170 >;
|
||||
|
||||
qcom,cpr-floor-to-ceiling-max-range =
|
||||
< 40000 40000 40000 40000 40000 40000>,
|
||||
< 40000 40000 40000 40000 40000 40000>,
|
||||
< 40000 40000 40000 40000 40000 40000>,
|
||||
< 40000 40000 40000 40000 40000 40000>,
|
||||
< 40000 40000 40000 40000 40000 40000>,
|
||||
< 40000 40000 40000 40000 40000 40000>,
|
||||
< 40000 40000 40000 40000 40000 40000>,
|
||||
< 40000 40000 40000 40000 40000 40000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
npu_cpr: npu-cpr {
|
||||
compatible = "qcom,cpr3-ipq807x-npu-regulator";
|
||||
reg = <0xa4000 0x1000>, <0x0193d008 0x4>;
|
||||
reg-names = "fuse_base", "cpr_tcsr_reg";
|
||||
qcom,cpr-ctrl-name = "npu";
|
||||
vdd-supply = <&s4>;
|
||||
qcom,voltage-step = <8000>;
|
||||
thread@0 {
|
||||
qcom,cpr-thread-id = <0>;
|
||||
qcom,cpr-consecutive-up = <0>;
|
||||
qcom,cpr-consecutive-down = <2>;
|
||||
qcom,cpr-up-threshold = <2>;
|
||||
qcom,cpr-down-threshold = <1>;
|
||||
|
||||
npu_vreg: regulator {
|
||||
regulator-name = "npu_corner";
|
||||
regulator-min-microvolt = <1>;
|
||||
regulator-max-microvolt = <3>;
|
||||
qcom,cpr-part-types = <2>;
|
||||
qcom,cpr-parts-voltage = <968000>;
|
||||
qcom,cpr-parts-voltage-v2 = <832001>;
|
||||
qcom,cpr-cold-temp-threshold-v2 = <30>;
|
||||
qcom,cpr-fuse-corners = <2>;
|
||||
qcom,cpr-fuse-combos = <1>;
|
||||
qcom,cpr-corners = <2>;
|
||||
qcom,cpr-speed-bins = <1>;
|
||||
qcom,cpr-speed-bin-corners = <2>;
|
||||
qcom,allow-voltage-interpolation;
|
||||
qcom,cpr-corner-fmax-map = <1 2>;
|
||||
qcom,cpr-voltage-ceiling =
|
||||
<912000 992000>;
|
||||
qcom,cpr-voltage-floor =
|
||||
<752000 792000>;
|
||||
qcom,corner-frequencies =
|
||||
<1497600000 1689600000>;
|
||||
|
||||
/* TT/FF parts i.e. turbo OL voltage < 968 mV */
|
||||
qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
|
||||
< 40000 40000>;
|
||||
|
||||
/* SS parts i.e turbo OL voltage >= 968 mV */
|
||||
qcom,cpr-open-loop-voltage-fuse-adjustment-1 =
|
||||
< 24000 24000>;
|
||||
|
||||
/* FF parts i.e. turbo OL voltage <= 832 mV */
|
||||
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0=
|
||||
<40000 40000>;
|
||||
|
||||
/* TT/SS parts i.e turbo OL voltage > 832 mV */
|
||||
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1=
|
||||
<40000 40000>;
|
||||
|
||||
/* FF parts i.e. turbo OL voltage <= 832 mV */
|
||||
qcom,cpr-cold-temp-voltage-adjustment-v2-0 =
|
||||
<0 0>;
|
||||
|
||||
/* TT/SS parts i.e turbo OL voltage > 832 mV */
|
||||
qcom,cpr-cold-temp-voltage-adjustment-v2-1 =
|
||||
<35000 27000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,531 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
&clocks {
|
||||
bias_pll_cc_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <300000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
bias_pll_nss_noc_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <416500000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
switch: ess-switch@3a000000 {
|
||||
compatible = "qcom,ess-switch-ipq807x";
|
||||
reg = <0x3a000000 0x1000000>;
|
||||
switch_access_mode = "local bus";
|
||||
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
|
||||
switch_inner_bmp = <0x80>; /*inner port bitmap*/
|
||||
clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
|
||||
<&gcc GCC_CMN_12GPLL_SYS_CLK>,
|
||||
<&gcc GCC_UNIPHY0_AHB_CLK>,
|
||||
<&gcc GCC_UNIPHY0_SYS_CLK>,
|
||||
<&gcc GCC_UNIPHY1_AHB_CLK>,
|
||||
<&gcc GCC_UNIPHY1_SYS_CLK>,
|
||||
<&gcc GCC_UNIPHY2_AHB_CLK>,
|
||||
<&gcc GCC_UNIPHY2_SYS_CLK>,
|
||||
<&gcc GCC_PORT1_MAC_CLK>,
|
||||
<&gcc GCC_PORT2_MAC_CLK>,
|
||||
<&gcc GCC_PORT3_MAC_CLK>,
|
||||
<&gcc GCC_PORT4_MAC_CLK>,
|
||||
<&gcc GCC_PORT5_MAC_CLK>,
|
||||
<&gcc GCC_PORT6_MAC_CLK>,
|
||||
<&gcc GCC_NSS_PPE_CLK>,
|
||||
<&gcc GCC_NSS_PPE_CFG_CLK>,
|
||||
<&gcc GCC_NSSNOC_PPE_CLK>,
|
||||
<&gcc GCC_NSSNOC_PPE_CFG_CLK>,
|
||||
<&gcc GCC_NSS_EDMA_CLK>,
|
||||
<&gcc GCC_NSS_EDMA_CFG_CLK>,
|
||||
<&gcc GCC_NSS_PPE_IPE_CLK>,
|
||||
<&gcc GCC_NSS_PPE_BTQ_CLK>,
|
||||
<&gcc GCC_MDIO_AHB_CLK>,
|
||||
<&gcc GCC_NSS_NOC_CLK>,
|
||||
<&gcc GCC_NSSNOC_SNOC_CLK>,
|
||||
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
|
||||
<&gcc GCC_NSS_CRYPTO_CLK>,
|
||||
<&gcc GCC_NSS_IMEM_CLK>,
|
||||
<&gcc GCC_NSS_PTP_REF_CLK>,
|
||||
<&gcc GCC_NSS_PORT1_RX_CLK>,
|
||||
<&gcc GCC_NSS_PORT1_TX_CLK>,
|
||||
<&gcc GCC_NSS_PORT2_RX_CLK>,
|
||||
<&gcc GCC_NSS_PORT2_TX_CLK>,
|
||||
<&gcc GCC_NSS_PORT3_RX_CLK>,
|
||||
<&gcc GCC_NSS_PORT3_TX_CLK>,
|
||||
<&gcc GCC_NSS_PORT4_RX_CLK>,
|
||||
<&gcc GCC_NSS_PORT4_TX_CLK>,
|
||||
<&gcc GCC_NSS_PORT5_RX_CLK>,
|
||||
<&gcc GCC_NSS_PORT5_TX_CLK>,
|
||||
<&gcc GCC_NSS_PORT6_RX_CLK>,
|
||||
<&gcc GCC_NSS_PORT6_TX_CLK>,
|
||||
<&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
|
||||
<&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
|
||||
<&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
|
||||
<&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
|
||||
<&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
|
||||
<&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
|
||||
<&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
|
||||
<&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
|
||||
<&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
|
||||
<&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
|
||||
<&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
|
||||
<&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
|
||||
<&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
|
||||
<&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
|
||||
<&gcc NSS_PORT5_RX_CLK_SRC>,
|
||||
<&gcc NSS_PORT5_TX_CLK_SRC>;
|
||||
clock-names = "cmn_ahb_clk", "cmn_sys_clk",
|
||||
"uniphy0_ahb_clk", "uniphy0_sys_clk",
|
||||
"uniphy1_ahb_clk", "uniphy1_sys_clk",
|
||||
"uniphy2_ahb_clk", "uniphy2_sys_clk",
|
||||
"port1_mac_clk", "port2_mac_clk",
|
||||
"port3_mac_clk", "port4_mac_clk",
|
||||
"port5_mac_clk", "port6_mac_clk",
|
||||
"nss_ppe_clk", "nss_ppe_cfg_clk",
|
||||
"nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
|
||||
"nss_edma_clk", "nss_edma_cfg_clk",
|
||||
"nss_ppe_ipe_clk", "nss_ppe_btq_clk",
|
||||
"gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
|
||||
"gcc_nssnoc_snoc_clk",
|
||||
"gcc_mem_noc_nss_axi_clk",
|
||||
"gcc_nss_crypto_clk",
|
||||
"gcc_nss_imem_clk",
|
||||
"gcc_nss_ptp_ref_clk",
|
||||
"nss_port1_rx_clk", "nss_port1_tx_clk",
|
||||
"nss_port2_rx_clk", "nss_port2_tx_clk",
|
||||
"nss_port3_rx_clk", "nss_port3_tx_clk",
|
||||
"nss_port4_rx_clk", "nss_port4_tx_clk",
|
||||
"nss_port5_rx_clk", "nss_port5_tx_clk",
|
||||
"nss_port6_rx_clk", "nss_port6_tx_clk",
|
||||
"uniphy0_port1_rx_clk",
|
||||
"uniphy0_port1_tx_clk",
|
||||
"uniphy0_port2_rx_clk",
|
||||
"uniphy0_port2_tx_clk",
|
||||
"uniphy0_port3_rx_clk",
|
||||
"uniphy0_port3_tx_clk",
|
||||
"uniphy0_port4_rx_clk",
|
||||
"uniphy0_port4_tx_clk",
|
||||
"uniphy0_port5_rx_clk",
|
||||
"uniphy0_port5_tx_clk",
|
||||
"uniphy1_port5_rx_clk",
|
||||
"uniphy1_port5_tx_clk",
|
||||
"uniphy2_port6_rx_clk",
|
||||
"uniphy2_port6_tx_clk",
|
||||
"nss_port5_rx_clk_src",
|
||||
"nss_port5_tx_clk_src";
|
||||
resets = <&gcc GCC_PPE_FULL_RESET>,
|
||||
<&gcc GCC_UNIPHY0_SOFT_RESET>,
|
||||
<&gcc GCC_UNIPHY0_XPCS_RESET>,
|
||||
<&gcc GCC_UNIPHY1_SOFT_RESET>,
|
||||
<&gcc GCC_UNIPHY1_XPCS_RESET>,
|
||||
<&gcc GCC_UNIPHY2_SOFT_RESET>,
|
||||
<&gcc GCC_UNIPHY2_XPCS_RESET>,
|
||||
<&gcc GCC_NSSPORT1_RESET>,
|
||||
<&gcc GCC_NSSPORT2_RESET>,
|
||||
<&gcc GCC_NSSPORT3_RESET>,
|
||||
<&gcc GCC_NSSPORT4_RESET>,
|
||||
<&gcc GCC_NSSPORT5_RESET>,
|
||||
<&gcc GCC_NSSPORT6_RESET>;
|
||||
reset-names = "ppe_rst", "uniphy0_soft_rst",
|
||||
"uniphy0_xpcs_rst", "uniphy1_soft_rst",
|
||||
"uniphy1_xpcs_rst", "uniphy2_soft_rst",
|
||||
"uniphy2_xpcs_rst", "nss_port1_rst",
|
||||
"nss_port2_rst", "nss_port3_rst",
|
||||
"nss_port4_rst", "nss_port5_rst",
|
||||
"nss_port6_rst";
|
||||
mdio-bus = <&mdio>;
|
||||
status = "disabled";
|
||||
|
||||
port_scheduler_resource {
|
||||
port@0 {
|
||||
port_id = <0>;
|
||||
ucast_queue = <0 143>;
|
||||
mcast_queue = <256 271>;
|
||||
l0sp = <0 35>;
|
||||
l0cdrr = <0 47>;
|
||||
l0edrr = <0 47>;
|
||||
l1cdrr = <0 7>;
|
||||
l1edrr = <0 7>;
|
||||
};
|
||||
port@1 {
|
||||
port_id = <1>;
|
||||
ucast_queue = <144 159>;
|
||||
mcast_queue = <272 275>;
|
||||
l0sp = <36 39>;
|
||||
l0cdrr = <48 63>;
|
||||
l0edrr = <48 63>;
|
||||
l1cdrr = <8 11>;
|
||||
l1edrr = <8 11>;
|
||||
};
|
||||
port@2 {
|
||||
port_id = <2>;
|
||||
ucast_queue = <160 175>;
|
||||
mcast_queue = <276 279>;
|
||||
l0sp = <40 43>;
|
||||
l0cdrr = <64 79>;
|
||||
l0edrr = <64 79>;
|
||||
l1cdrr = <12 15>;
|
||||
l1edrr = <12 15>;
|
||||
};
|
||||
port@3 {
|
||||
port_id = <3>;
|
||||
ucast_queue = <176 191>;
|
||||
mcast_queue = <280 283>;
|
||||
l0sp = <44 47>;
|
||||
l0cdrr = <80 95>;
|
||||
l0edrr = <80 95>;
|
||||
l1cdrr = <16 19>;
|
||||
l1edrr = <16 19>;
|
||||
};
|
||||
port@4 {
|
||||
port_id = <4>;
|
||||
ucast_queue = <192 207>;
|
||||
mcast_queue = <284 287>;
|
||||
l0sp = <48 51>;
|
||||
l0cdrr = <96 111>;
|
||||
l0edrr = <96 111>;
|
||||
l1cdrr = <20 23>;
|
||||
l1edrr = <20 23>;
|
||||
};
|
||||
port@5 {
|
||||
port_id = <5>;
|
||||
ucast_queue = <208 223>;
|
||||
mcast_queue = <288 291>;
|
||||
l0sp = <52 55>;
|
||||
l0cdrr = <112 127>;
|
||||
l0edrr = <112 127>;
|
||||
l1cdrr = <24 27>;
|
||||
l1edrr = <24 27>;
|
||||
};
|
||||
port@6 {
|
||||
port_id = <6>;
|
||||
ucast_queue = <224 239>;
|
||||
mcast_queue = <292 295>;
|
||||
l0sp = <56 59>;
|
||||
l0cdrr = <128 143>;
|
||||
l0edrr = <128 143>;
|
||||
l1cdrr = <28 31>;
|
||||
l1edrr = <28 31>;
|
||||
};
|
||||
port@7 {
|
||||
port_id = <7>;
|
||||
ucast_queue = <240 255>;
|
||||
mcast_queue = <296 299>;
|
||||
l0sp = <60 63>;
|
||||
l0cdrr = <144 159>;
|
||||
l0edrr = <144 159>;
|
||||
l1cdrr = <32 35>;
|
||||
l1edrr = <32 35>;
|
||||
};
|
||||
};
|
||||
port_scheduler_config {
|
||||
port@0 {
|
||||
port_id = <0>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <0 1>; /*L0 SPs*/
|
||||
/*cpri cdrr epri edrr*/
|
||||
cfg = <0 0 0 0>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
/*unicast queues*/
|
||||
ucast_queue = <0 4 8>;
|
||||
/*multicast queues*/
|
||||
mcast_queue = <256 260>;
|
||||
/*sp cpri cdrr epri edrr*/
|
||||
cfg = <0 0 0 0 0>;
|
||||
};
|
||||
group@1 {
|
||||
ucast_queue = <1 5 9>;
|
||||
mcast_queue = <257 261>;
|
||||
cfg = <0 1 1 1 1>;
|
||||
};
|
||||
group@2 {
|
||||
ucast_queue = <2 6 10>;
|
||||
mcast_queue = <258 262>;
|
||||
cfg = <0 2 2 2 2>;
|
||||
};
|
||||
group@3 {
|
||||
ucast_queue = <3 7 11>;
|
||||
mcast_queue = <259 263>;
|
||||
cfg = <0 3 3 3 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
port_id = <1>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <36>;
|
||||
cfg = <0 8 0 8>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <37>;
|
||||
cfg = <1 9 1 9>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <144>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <272>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <36 0 48 0 48>;
|
||||
};
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
port_id = <2>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <40>;
|
||||
cfg = <0 12 0 12>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <41>;
|
||||
cfg = <1 13 1 13>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <160>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <276>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <40 0 64 0 64>;
|
||||
};
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
port_id = <3>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <44>;
|
||||
cfg = <0 16 0 16>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <45>;
|
||||
cfg = <1 17 1 17>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <176>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <280>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <44 0 80 0 80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
port@4 {
|
||||
port_id = <4>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <48>;
|
||||
cfg = <0 20 0 20>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <49>;
|
||||
cfg = <1 21 1 21>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <192>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <284>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <48 0 96 0 96>;
|
||||
};
|
||||
};
|
||||
};
|
||||
port@5 {
|
||||
port_id = <5>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <52>;
|
||||
cfg = <0 24 0 24>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <53>;
|
||||
cfg = <1 25 1 25>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <208>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <288>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <52 0 112 0 112>;
|
||||
};
|
||||
};
|
||||
};
|
||||
port@6 {
|
||||
port_id = <6>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <56>;
|
||||
cfg = <0 28 0 28>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <57>;
|
||||
cfg = <1 29 1 29>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <224>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <292>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <56 0 128 0 128>;
|
||||
};
|
||||
};
|
||||
};
|
||||
port@7 {
|
||||
port_id = <7>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <60>;
|
||||
cfg = <0 32 0 32>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <61>;
|
||||
cfg = <1 33 1 33>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <240>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <296>;
|
||||
cfg = <60 0 144 0 144>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ess-uniphy@7a00000 {
|
||||
compatible = "qcom,ess-uniphy";
|
||||
reg = <0x7a00000 0x30000>;
|
||||
uniphy_access_mode = "local bus";
|
||||
};
|
||||
|
||||
edma: edma@3ab00000 {
|
||||
compatible = "qcom,edma";
|
||||
reg = <0x3ab00000 0x76900>;
|
||||
reg-names = "edma-reg-base";
|
||||
qcom,txdesc-ring-start = <23>;
|
||||
qcom,txdesc-rings = <1>;
|
||||
qcom,txcmpl-ring-start = <7>;
|
||||
qcom,txcmpl-rings = <1>;
|
||||
qcom,rxfill-ring-start = <7>;
|
||||
qcom,rxfill-rings = <1>;
|
||||
qcom,rxdesc-ring-start = <15>;
|
||||
qcom,rxdesc-rings = <1>;
|
||||
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&gcc GCC_EDMA_HW_RESET>;
|
||||
reset-names = "edma_rst";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dp1: dp1 {
|
||||
device_type = "network";
|
||||
compatible = "qcom,nss-dp";
|
||||
qcom,id = <1>;
|
||||
reg = <0x3a001000 0x200>;
|
||||
qcom,mactype = <0>;
|
||||
local-mac-address = [000000000000];
|
||||
phy-mode = "sgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dp2: dp2 {
|
||||
device_type = "network";
|
||||
compatible = "qcom,nss-dp";
|
||||
qcom,id = <2>;
|
||||
reg = <0x3a001200 0x200>;
|
||||
qcom,mactype = <0>;
|
||||
local-mac-address = [000000000000];
|
||||
phy-mode = "sgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dp3: dp3 {
|
||||
device_type = "network";
|
||||
compatible = "qcom,nss-dp";
|
||||
qcom,id = <3>;
|
||||
reg = <0x3a001400 0x200>;
|
||||
qcom,mactype = <0>;
|
||||
local-mac-address = [000000000000];
|
||||
phy-mode = "sgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dp4: dp4 {
|
||||
device_type = "network";
|
||||
compatible = "qcom,nss-dp";
|
||||
qcom,id = <4>;
|
||||
reg = <0x3a001600 0x200>;
|
||||
qcom,mactype = <0>;
|
||||
local-mac-address = [000000000000];
|
||||
phy-mode = "sgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dp5: dp5 {
|
||||
device_type = "network";
|
||||
compatible = "qcom,nss-dp";
|
||||
qcom,id = <5>;
|
||||
reg = <0x3a001800 0x200>;
|
||||
qcom,mactype = <0>;
|
||||
local-mac-address = [000000000000];
|
||||
phy-mode = "sgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dp6: dp6 {
|
||||
device_type = "network";
|
||||
compatible = "qcom,nss-dp";
|
||||
qcom,id = <6>;
|
||||
reg = <0x3a001a00 0x200>;
|
||||
qcom,mactype = <0>;
|
||||
local-mac-address = [000000000000];
|
||||
phy-mode = "sgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dp5_syn: dp5-syn {
|
||||
device_type = "network";
|
||||
compatible = "qcom,nss-dp";
|
||||
qcom,id = <5>;
|
||||
reg = <0x3a003000 0x3fff>;
|
||||
qcom,mactype = <1>;
|
||||
local-mac-address = [000000000000];
|
||||
phy-mode = "sgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dp6_syn: dp6-syn {
|
||||
device_type = "network";
|
||||
compatible = "qcom,nss-dp";
|
||||
qcom,id = <6>;
|
||||
reg = <0x3a007000 0x3fff>;
|
||||
qcom,mactype = <1>;
|
||||
local-mac-address = [000000000000];
|
||||
phy-mode = "sgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,188 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include "ipq8074-cpr-regulator.dtsi"
|
||||
|
||||
&CPU0 {
|
||||
cpu-supply = <&apc_vreg>;
|
||||
voltage-tolerance = <1>;
|
||||
};
|
||||
|
||||
&CPU1 {
|
||||
cpu-supply = <&apc_vreg>;
|
||||
voltage-tolerance = <1>;
|
||||
};
|
||||
|
||||
&CPU2 {
|
||||
cpu-supply = <&apc_vreg>;
|
||||
voltage-tolerance = <1>;
|
||||
};
|
||||
|
||||
&CPU3 {
|
||||
cpu-supply = <&apc_vreg>;
|
||||
voltage-tolerance = <1>;
|
||||
};
|
||||
&cpu0_thermal {
|
||||
trips {
|
||||
cpu0_passive_low: cpu-passive-low {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu0_passive_high: cpu-passive-high {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu0_passive_low>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cpu0_passive_high>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu1_thermal {
|
||||
trips {
|
||||
cpu1_passive_low: cpu-passive-low {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu1_passive_high: cpu-passive-high {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu1_passive_low>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cpu1_passive_high>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu2_thermal {
|
||||
trips {
|
||||
cpu2_passive_low: cpu-passive-low {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu2_passive_high: cpu-passive-high {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu2_passive_low>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cpu2_passive_high>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu3_thermal {
|
||||
trips {
|
||||
cpu3_passive_low: cpu-passive-low {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu3_passive_high: cpu-passive-high {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu3_passive_low>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cpu3_passive_high>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cluster_thermal {
|
||||
trips {
|
||||
cluster_passive_low: cluster-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cluster_passive_high: cluster-passive-high {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cluster_passive_low>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cluster_passive_high>;
|
||||
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,445 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright (c) 2022, Karol Przybylski <itor@o2.pl>
|
||||
* Copyright (c) 2023, Andre Valentin <avalentin@marcant.net>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8074.dtsi"
|
||||
#include "ipq8074-hk-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
|
||||
/ {
|
||||
model = "Zyxel NBG7815";
|
||||
compatible = "zyxel,nbg7815", "qcom,ipq8074";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
serial1 = &blsp1_uart3;
|
||||
/* Alias as required by u-boot to patch MAC addresses */
|
||||
ethernet0 = &dp1;
|
||||
label-mac-device = &dp1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-pins {
|
||||
mdc {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&blsp1_uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&prng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
&blsp1_spi1 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <0>;
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Bootloader will find the NAND DT node by the compatible and
|
||||
* then "fixup" it by adding the partitions from the SMEM table
|
||||
* using the legacy bindings thus making it impossible for us
|
||||
* to change the partition table or utilize NVMEM for calibration.
|
||||
* So add a dummy partitions node that bootloader will populate
|
||||
* and set it as disabled so the kernel ignores it instead of
|
||||
* printing warnings due to the broken way bootloader adds the
|
||||
* partitions.
|
||||
*/
|
||||
partitions {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "0:sbl1";
|
||||
reg = <0x0 0x50000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@50000 {
|
||||
label = "0:mibib";
|
||||
reg = <0x50000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "0:bootconfig";
|
||||
reg = <0x60000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "0:bootconfig1";
|
||||
reg = <0x80000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@a0000 {
|
||||
label = "0:qsee";
|
||||
reg = <0xa0000 0x180000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@220000 {
|
||||
label = "0:qsee_1";
|
||||
reg = <0x220000 0x180000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3a0000 {
|
||||
label = "0:devcfg";
|
||||
reg = <0x3a0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3b0000 {
|
||||
label = "0:devcfg_1";
|
||||
reg = <0x3b0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3c0000 {
|
||||
label = "0:apdp";
|
||||
reg = <0x3c0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3d0000 {
|
||||
label = "0:apdp_1";
|
||||
reg = <0x3d0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3e0000 {
|
||||
label = "0:rpm";
|
||||
reg = <0x3e0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@420000 {
|
||||
label = "0:rpm_1";
|
||||
reg = <0x420000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@460000 {
|
||||
label = "0:cdt";
|
||||
reg = <0x460000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@470000 {
|
||||
label = "0:cdt_1";
|
||||
reg = <0x470000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@480000 {
|
||||
label = "0:appsbl";
|
||||
reg = <0x480000 0xc0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@540000 {
|
||||
label = "0:appsbl_1";
|
||||
reg = <0x540000 0xc0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@600000 {
|
||||
compatible = "u-boot,env";
|
||||
label = "0:appsblenv";
|
||||
reg = <0x600000 0x10000>;
|
||||
|
||||
macaddr_lan: ethaddr {
|
||||
#nvmem-cell-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
partition@610000 {
|
||||
label = "0:art";
|
||||
reg = <0x610000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@650000 {
|
||||
label = "0:ethphyfw";
|
||||
reg = <0x650000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@6d0000 {
|
||||
label = "0:crt";
|
||||
reg = <0x6d0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@6e0000 {
|
||||
label = "dual_flag";
|
||||
reg = <0x6e0000 0x10000>;
|
||||
};
|
||||
|
||||
partition@6f0000 {
|
||||
label = "reserved";
|
||||
reg = <0x6f0000 0x110000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
|
||||
|
||||
qca8075_1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
qca8075_2: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
qca8075_3: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
qca8075_4: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
qca8081: ethernet-phy@4{
|
||||
compatible = "ethernet-phy-id004d.d101";
|
||||
reg = <28>;
|
||||
reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
aqr113c: ethernet-phy@5 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <8>;
|
||||
reset-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>;
|
||||
switch_lan_bmp = <0x3e>;
|
||||
switch_wan_bmp = <0x40>;
|
||||
switch_mac_mode = <0x0>;
|
||||
switch_mac_mode1 = <0xf>;
|
||||
switch_mac_mode2 = <0xd>;
|
||||
bm_tick_mode = <0>;
|
||||
tm_tick_mode = <0>;
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@0 {
|
||||
port_id = <1>;
|
||||
phy_address = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
port_id = <2>;
|
||||
phy_address = <1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
port_id = <3>;
|
||||
phy_address = <2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
port_id = <4>;
|
||||
phy_address = <3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
port_id = <5>;
|
||||
phy_address = <28>;
|
||||
port_mac_sel = "QGMAC_PORT";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
port_id = <6>;
|
||||
ethernet-phy-ieee802.3-c45;
|
||||
phy_address = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp1 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_1>;
|
||||
label = "lan1";
|
||||
nvmem-cells = <&macaddr_lan 0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp2 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_2>;
|
||||
label = "lan2";
|
||||
nvmem-cells = <&macaddr_lan 0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp3 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_3>;
|
||||
label = "lan3";
|
||||
nvmem-cells = <&macaddr_lan 0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp4 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_4>;
|
||||
label = "lan4";
|
||||
nvmem-cells = <&macaddr_lan 0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp5 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8081>;
|
||||
label = "wan";
|
||||
nvmem-cells = <&macaddr_lan 1>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp6_syn {
|
||||
status = "okay";
|
||||
phy-handle = <&aqr113c>;
|
||||
label = "10g";
|
||||
nvmem-cells = <&macaddr_lan 0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&blsp1_i2c2 {
|
||||
pinctrl-0 = <&i2c_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
tmp103@70 {
|
||||
compatible = "ti,tmp103";
|
||||
reg = <0x70>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
/* unstable, problem with the hs400 > h200 speed switch */
|
||||
/delete-property/ mmc-hs400-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-ddr-1_8v;
|
||||
vqmmc-supply = <&l11>;
|
||||
};
|
||||
|
||||
&ssphy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qusb_phy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssphy_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qusb_phy_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
qcom,ath11k-calibration-variant = "Zyxel-NBG7815";
|
||||
};
|
||||
@@ -0,0 +1,376 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq8074.dtsi"
|
||||
#include "ipq8074-hk-cpu.dtsi"
|
||||
#include "ipq8074-ess.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Buffalo WXR-5950AX12";
|
||||
compatible = "buffalo,wxr-5950ax12", "qcom,ipq8074";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
led-boot = &led_power_white;
|
||||
led-failsafe = &led_power_red;
|
||||
led-running = &led_power_white;
|
||||
led-upgrade = &led_power_white;
|
||||
label-mac-device = &dp5_syn;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs-append = " ubi.mtd=user_property root=/dev/ubiblock1_0";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
label = "white:router";
|
||||
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
};
|
||||
|
||||
led-1 {
|
||||
label = "red:router";
|
||||
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led_power_red: led-2 {
|
||||
label = "red:power";
|
||||
gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_POWER;
|
||||
};
|
||||
|
||||
led_power_white: led-3 {
|
||||
label = "white:power";
|
||||
gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
function = LED_FUNCTION_POWER;
|
||||
};
|
||||
|
||||
led-4 {
|
||||
label = "white:internet";
|
||||
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
};
|
||||
|
||||
led-5 {
|
||||
label = "red:internet";
|
||||
gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led-6 {
|
||||
label = "red:wireless";
|
||||
gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_WLAN;
|
||||
};
|
||||
|
||||
led-7 {
|
||||
label = "white:wireless";
|
||||
gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
function = LED_FUNCTION_WLAN;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
/*
|
||||
* mode: 3x position switch
|
||||
*
|
||||
* - ROUTER
|
||||
* - AP
|
||||
* - WB (Wireless Bridge)
|
||||
*/
|
||||
ap {
|
||||
label = "mode-ap";
|
||||
gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <BTN_0>;
|
||||
};
|
||||
|
||||
bridge {
|
||||
label = "mode-wb";
|
||||
gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <BTN_1>;
|
||||
};
|
||||
|
||||
/*
|
||||
* op: 2x position switch
|
||||
*
|
||||
* - AUTO
|
||||
* - MANUAL (select Router/AP/WB manually)
|
||||
*/
|
||||
manual {
|
||||
label = "op-manual";
|
||||
gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <BTN_2>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_usb_vbus: regulator-5v-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&tlmm 64 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio-pins {
|
||||
mdc {
|
||||
pins = "gpio68";
|
||||
function = "mdc";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdio {
|
||||
pins = "gpio69";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&prng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qpic_nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
partitions {
|
||||
compatible = "qcom,smem-part";
|
||||
|
||||
partition-0-appsblenv {
|
||||
compatible = "fixed-partitions";
|
||||
label = "0:appsblenv";
|
||||
read-only;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
compatible = "u-boot,env";
|
||||
label = "env-data";
|
||||
reg = <0x0 0x40000>;
|
||||
|
||||
macaddr_appsblenv_ethaddr: ethaddr {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* RESET pins of phy chips
|
||||
*
|
||||
* WXR-5950AX12 has 2x RESET pins for QCA8075 and AQR113C.
|
||||
* The pin of QCA8075 is for the chip and not phys in the chip, the
|
||||
* pin of AQR113C is for 2x chips. So both pins are not appropriate
|
||||
* to declare them as reset-gpios in phy nodes.
|
||||
* Multiple entries in reset-gpios of mdio may not be supported, but
|
||||
* leave the following as-is to show that the those reset pin exists.
|
||||
*/
|
||||
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>, /* QCA8075 RESET */
|
||||
<&tlmm 63 GPIO_ACTIVE_LOW>; /* AQR113C RESET (2x) */
|
||||
|
||||
aqr113c_1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
aqr113c_2: ethernet-phy@8 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x8>;
|
||||
};
|
||||
|
||||
qca8075_1: ethernet-phy@18 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x18>;
|
||||
};
|
||||
|
||||
qca8075_2: ethernet-phy@19 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x19>;
|
||||
};
|
||||
|
||||
qca8075_3: ethernet-phy@1a {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
|
||||
qca8075_4: ethernet-phy@1b {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1b>;
|
||||
};
|
||||
|
||||
qca8075_5: ethernet-phy@1c {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1c>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
switch_cpu_bmp = <0x1>;
|
||||
switch_lan_bmp = <0x3e>;
|
||||
switch_wan_bmp = <0x40>;
|
||||
switch_mac_mode = <0xb>;
|
||||
switch_mac_mode1 = <0xd>;
|
||||
switch_mac_mode2 = <0xd>;
|
||||
bm_tick_mode = <0>;
|
||||
tm_tick_mode = <0>;
|
||||
|
||||
qcom,port_phyinfo {
|
||||
port@0 {
|
||||
port_id = <1>;
|
||||
phy_address = <0x18>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
port_id = <2>;
|
||||
phy_address = <0x19>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
port_id = <3>;
|
||||
phy_address = <0x1a>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
port_id = <4>;
|
||||
phy_address = <0x1b>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
port_id = <5>;
|
||||
ethernet-phy-ieee802.3-c45;
|
||||
phy_address = <0x0>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
port_id = <6>;
|
||||
ethernet-phy-ieee802.3-c45;
|
||||
phy_address = <0x8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp2 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_2>;
|
||||
label = "lan4";
|
||||
nvmem-cells = <&macaddr_appsblenv_ethaddr>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp3 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_3>;
|
||||
label = "lan3";
|
||||
nvmem-cells = <&macaddr_appsblenv_ethaddr>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp4 {
|
||||
status = "okay";
|
||||
phy-handle = <&qca8075_4>;
|
||||
label = "lan2";
|
||||
nvmem-cells = <&macaddr_appsblenv_ethaddr>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp5_syn {
|
||||
status = "okay";
|
||||
phy-handle = <&aqr113c_1>;
|
||||
label = "wan";
|
||||
nvmem-cells = <&macaddr_appsblenv_ethaddr>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&dp6_syn {
|
||||
status = "okay";
|
||||
phy-handle = <&aqr113c_2>;
|
||||
label = "lan1";
|
||||
nvmem-cells = <&macaddr_appsblenv_ethaddr>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&ssphy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qusb_phy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0 {
|
||||
status = "okay";
|
||||
|
||||
vbus-supply = <®_usb_vbus>;
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
qcom,ath11k-calibration-variant = "Buffalo-WXR-5950AX12";
|
||||
};
|
||||
1
target/linux/qualcommax/generic/target.mk
Normal file
1
target/linux/qualcommax/generic/target.mk
Normal file
@@ -0,0 +1 @@
|
||||
BOARDNAME:=Generic
|
||||
17
target/linux/qualcommax/image/Makefile
Normal file
17
target/linux/qualcommax/image/Makefile
Normal file
@@ -0,0 +1,17 @@
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
define Device/Default
|
||||
PROFILES := Default
|
||||
KERNEL_LOADADDR := 0x41000000
|
||||
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
|
||||
DEVICE_DTS_CONFIG := config@1
|
||||
DEVICE_DTS_DIR := $(DTS_DIR)/qcom
|
||||
IMAGES := sysupgrade.bin
|
||||
IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata
|
||||
IMAGE/sysupgrade.bin/squashfs :=
|
||||
endef
|
||||
|
||||
include $(SUBTARGET).mk
|
||||
|
||||
$(eval $(call BuildImage))
|
||||
188
target/linux/qualcommax/image/generic.mk
Normal file
188
target/linux/qualcommax/image/generic.mk
Normal file
@@ -0,0 +1,188 @@
|
||||
define Device/FitImage
|
||||
KERNEL_SUFFIX := -uImage.itb
|
||||
KERNEL = kernel-bin | libdeflate-gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb
|
||||
KERNEL_NAME := Image
|
||||
endef
|
||||
|
||||
define Device/FitImageLzma
|
||||
KERNEL_SUFFIX := -uImage.itb
|
||||
KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb
|
||||
KERNEL_NAME := Image
|
||||
endef
|
||||
|
||||
define Device/EmmcImage
|
||||
IMAGES += factory.bin sysupgrade.bin
|
||||
IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 64k
|
||||
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to 64k | sysupgrade-tar rootfs=$$$$@ | append-metadata
|
||||
endef
|
||||
|
||||
define Device/UbiFit
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGES := factory.ubi sysupgrade.bin
|
||||
IMAGE/factory.ubi := append-ubi
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
|
||||
define Device/buffalo_wxr-5950ax12
|
||||
$(call Device/FitImage)
|
||||
DEVICE_VENDOR := Buffalo
|
||||
DEVICE_MODEL := WXR-5950AX12
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_DTS_CONFIG := config@hk01
|
||||
SOC := ipq8074
|
||||
IMAGES := sysupgrade.bin
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
DEVICE_PACKAGES := ipq-wifi-buffalo_wxr-5950ax12
|
||||
endef
|
||||
TARGET_DEVICES += buffalo_wxr-5950ax12
|
||||
|
||||
define Device/compex_wpq873
|
||||
$(call Device/FitImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_VENDOR := Compex
|
||||
DEVICE_MODEL := WPQ873
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_DTS_CONFIG := config@hk09.wpq873
|
||||
SOC := ipq8072
|
||||
IMAGE/factory.ubi := append-ubi | qsdk-ipq-factory-nand
|
||||
endef
|
||||
TARGET_DEVICES += compex_wpq873
|
||||
|
||||
define Device/dynalink_dl-wrx36
|
||||
$(call Device/FitImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_VENDOR := Dynalink
|
||||
DEVICE_MODEL := DL-WRX36
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_DTS_CONFIG := config@rt5010w-d350-rev0
|
||||
SOC := ipq8072
|
||||
DEVICE_PACKAGES := ipq-wifi-dynalink_dl-wrx36
|
||||
endef
|
||||
TARGET_DEVICES += dynalink_dl-wrx36
|
||||
|
||||
define Device/edgecore_eap102
|
||||
$(call Device/FitImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_VENDOR := Edgecore
|
||||
DEVICE_MODEL := EAP102
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_DTS_CONFIG := config@ac02
|
||||
SOC := ipq8071
|
||||
DEVICE_PACKAGES := ipq-wifi-edgecore_eap102
|
||||
IMAGE/factory.ubi := append-ubi | qsdk-ipq-factory-nand
|
||||
endef
|
||||
TARGET_DEVICES += edgecore_eap102
|
||||
|
||||
define Device/edimax_cax1800
|
||||
$(call Device/FitImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_VENDOR := Edimax
|
||||
DEVICE_MODEL := CAX1800
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_DTS_CONFIG := config@ac03
|
||||
SOC := ipq8070
|
||||
DEVICE_PACKAGES := ipq-wifi-edimax_cax1800
|
||||
endef
|
||||
TARGET_DEVICES += edimax_cax1800
|
||||
|
||||
define Device/netgear_wax218
|
||||
$(call Device/FitImage)
|
||||
$(call Device/UbiFit)
|
||||
ARTIFACTS := web-ui-factory.fit
|
||||
DEVICE_VENDOR := Netgear
|
||||
DEVICE_MODEL := WAX218
|
||||
DEVICE_DTS_CONFIG := config@hk07
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
SOC := ipq8072
|
||||
ARTIFACT/web-ui-factory.fit := append-image initramfs-uImage.itb | \
|
||||
ubinize-kernel | qsdk-ipq-factory-nand
|
||||
DEVICE_PACKAGES := kmod-spi-gpio kmod-spi-bitbang kmod-gpio-nxp-74hc164 \
|
||||
ipq-wifi-netgear_wax218
|
||||
endef
|
||||
TARGET_DEVICES += netgear_wax218
|
||||
|
||||
define Device/prpl_haze
|
||||
$(call Device/FitImage)
|
||||
$(call Device/EmmcImage)
|
||||
DEVICE_VENDOR := prpl Foundation
|
||||
DEVICE_MODEL := Haze
|
||||
DEVICE_DTS_CONFIG := config@hk09
|
||||
SOC := ipq8072
|
||||
DEVICE_PACKAGES += ath11k-firmware-qcn9074 ipq-wifi-prpl_haze kmod-ath11k-pci
|
||||
endef
|
||||
TARGET_DEVICES += prpl_haze
|
||||
|
||||
define Device/qnap_301w
|
||||
$(call Device/FitImage)
|
||||
$(call Device/EmmcImage)
|
||||
DEVICE_VENDOR := QNAP
|
||||
DEVICE_MODEL := 301w
|
||||
DEVICE_DTS_CONFIG := config@hk01
|
||||
KERNEL_SIZE := 16384k
|
||||
SOC := ipq8072
|
||||
DEVICE_PACKAGES += ipq-wifi-qnap_301w
|
||||
endef
|
||||
TARGET_DEVICES += qnap_301w
|
||||
|
||||
define Device/redmi_ax6
|
||||
$(call Device/xiaomi_ax3600)
|
||||
DEVICE_VENDOR := Redmi
|
||||
DEVICE_MODEL := AX6
|
||||
DEVICE_PACKAGES := ipq-wifi-redmi_ax6
|
||||
endef
|
||||
TARGET_DEVICES += redmi_ax6
|
||||
|
||||
define Device/xiaomi_ax3600
|
||||
$(call Device/FitImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_VENDOR := Xiaomi
|
||||
DEVICE_MODEL := AX3600
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_DTS_CONFIG := config@ac04
|
||||
SOC := ipq8071
|
||||
KERNEL_SIZE := 36608k
|
||||
DEVICE_PACKAGES := ipq-wifi-xiaomi_ax3600 kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9887-ct
|
||||
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
|
||||
ARTIFACTS := initramfs-factory.ubi
|
||||
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-uImage.itb | ubinize-kernel
|
||||
endif
|
||||
endef
|
||||
TARGET_DEVICES += xiaomi_ax3600
|
||||
|
||||
define Device/xiaomi_ax9000
|
||||
$(call Device/FitImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_VENDOR := Xiaomi
|
||||
DEVICE_MODEL := AX9000
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_DTS_CONFIG := config@hk14
|
||||
SOC := ipq8072
|
||||
KERNEL_SIZE := 57344k
|
||||
DEVICE_PACKAGES := ipq-wifi-xiaomi_ax9000 kmod-ath11k-pci ath11k-firmware-qcn9074 \
|
||||
kmod-ath10k-ct ath10k-firmware-qca9887-ct
|
||||
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
|
||||
ARTIFACTS := initramfs-factory.ubi
|
||||
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-uImage.itb | ubinize-kernel
|
||||
endif
|
||||
endef
|
||||
TARGET_DEVICES += xiaomi_ax9000
|
||||
|
||||
define Device/zyxel_nbg7815
|
||||
$(call Device/FitImage)
|
||||
$(call Device/EmmcImage)
|
||||
DEVICE_VENDOR := ZYXEL
|
||||
DEVICE_MODEL := NBG7815
|
||||
DEVICE_DTS_CONFIG := config@nbg7815
|
||||
SOC := ipq8074
|
||||
DEVICE_PACKAGES += ipq-wifi-zyxel_nbg7815 kmod-ath11k-pci kmod-hwmon-tmp103 \
|
||||
kmod-bluetooth
|
||||
endef
|
||||
TARGET_DEVICES += zyxel_nbg7815
|
||||
@@ -0,0 +1,32 @@
|
||||
From 6463c10bfdbd684ec7ecfd408ea541283215a088 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 19 Aug 2022 00:06:28 +0200
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: add A53 PLL node
|
||||
|
||||
Add the required node for A53 PLL which will be used to provide the CPU
|
||||
clock via APCS for APSS scaling.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20220818220628.339366-9-robimarko@gmail.com
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -675,6 +675,14 @@
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
+ a53pll: clock@b116000 {
|
||||
+ compatible = "qcom,ipq8074-a53pll";
|
||||
+ reg = <0x0b116000 0x40>;
|
||||
+ #clock-cells = <0>;
|
||||
+ clocks = <&xo>;
|
||||
+ clock-names = "xo";
|
||||
+ };
|
||||
+
|
||||
timer@b120000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@@ -0,0 +1,134 @@
|
||||
From e593e834fe8ba9bf314d8215ac05d8787f81efda Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 19 Aug 2022 00:02:42 +0200
|
||||
Subject: [PATCH] thermal/drivers/tsens: Add support for combined interrupt
|
||||
|
||||
Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
|
||||
signaling both up/low and critical trips.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20220818220245.338396-2-robimarko@gmail.com
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
---
|
||||
drivers/thermal/qcom/tsens-8960.c | 1 +
|
||||
drivers/thermal/qcom/tsens-v0_1.c | 1 +
|
||||
drivers/thermal/qcom/tsens-v1.c | 1 +
|
||||
drivers/thermal/qcom/tsens-v2.c | 1 +
|
||||
drivers/thermal/qcom/tsens.c | 38 ++++++++++++++++++++++++++-----
|
||||
drivers/thermal/qcom/tsens.h | 2 ++
|
||||
6 files changed, 38 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/thermal/qcom/tsens-8960.c
|
||||
+++ b/drivers/thermal/qcom/tsens-8960.c
|
||||
@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
|
||||
static struct tsens_features tsens_8960_feat = {
|
||||
.ver_major = VER_0,
|
||||
.crit_int = 0,
|
||||
+ .combo_int = 0,
|
||||
.adc = 1,
|
||||
.srot_split = 0,
|
||||
.max_sensors = 11,
|
||||
--- a/drivers/thermal/qcom/tsens-v0_1.c
|
||||
+++ b/drivers/thermal/qcom/tsens-v0_1.c
|
||||
@@ -549,6 +549,7 @@ static int __init init_8939(struct tsens
|
||||
static struct tsens_features tsens_v0_1_feat = {
|
||||
.ver_major = VER_0_1,
|
||||
.crit_int = 0,
|
||||
+ .combo_int = 0,
|
||||
.adc = 1,
|
||||
.srot_split = 1,
|
||||
.max_sensors = 11,
|
||||
--- a/drivers/thermal/qcom/tsens-v1.c
|
||||
+++ b/drivers/thermal/qcom/tsens-v1.c
|
||||
@@ -273,6 +273,7 @@ static int calibrate_8976(struct tsens_p
|
||||
static struct tsens_features tsens_v1_feat = {
|
||||
.ver_major = VER_1_X,
|
||||
.crit_int = 0,
|
||||
+ .combo_int = 0,
|
||||
.adc = 1,
|
||||
.srot_split = 1,
|
||||
.max_sensors = 11,
|
||||
--- a/drivers/thermal/qcom/tsens-v2.c
|
||||
+++ b/drivers/thermal/qcom/tsens-v2.c
|
||||
@@ -31,6 +31,7 @@
|
||||
static struct tsens_features tsens_v2_feat = {
|
||||
.ver_major = VER_2_X,
|
||||
.crit_int = 1,
|
||||
+ .combo_int = 0,
|
||||
.adc = 0,
|
||||
.srot_split = 1,
|
||||
.max_sensors = 16,
|
||||
--- a/drivers/thermal/qcom/tsens.c
|
||||
+++ b/drivers/thermal/qcom/tsens.c
|
||||
@@ -532,6 +532,27 @@ static irqreturn_t tsens_irq_thread(int
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
+/**
|
||||
+ * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
|
||||
+ * @irq: irq number
|
||||
+ * @data: tsens controller private data
|
||||
+ *
|
||||
+ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
|
||||
+ * critical handler first and then the up/low one.
|
||||
+ *
|
||||
+ * Return: IRQ_HANDLED
|
||||
+ */
|
||||
+static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
|
||||
+{
|
||||
+ irqreturn_t ret;
|
||||
+
|
||||
+ ret = tsens_critical_irq_thread(irq, data);
|
||||
+ if (ret != IRQ_HANDLED)
|
||||
+ return ret;
|
||||
+
|
||||
+ return tsens_irq_thread(irq, data);
|
||||
+}
|
||||
+
|
||||
static int tsens_set_trips(struct thermal_zone_device *tz, int low, int high)
|
||||
{
|
||||
struct tsens_sensor *s = tz->devdata;
|
||||
@@ -1074,13 +1095,18 @@ static int tsens_register(struct tsens_p
|
||||
tsens_mC_to_hw(priv->sensor, 0));
|
||||
}
|
||||
|
||||
- ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
|
||||
- if (ret < 0)
|
||||
- return ret;
|
||||
+ if (priv->feat->combo_int) {
|
||||
+ ret = tsens_register_irq(priv, "combined",
|
||||
+ tsens_combined_irq_thread);
|
||||
+ } else {
|
||||
+ ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
|
||||
- if (priv->feat->crit_int)
|
||||
- ret = tsens_register_irq(priv, "critical",
|
||||
- tsens_critical_irq_thread);
|
||||
+ if (priv->feat->crit_int)
|
||||
+ ret = tsens_register_irq(priv, "critical",
|
||||
+ tsens_critical_irq_thread);
|
||||
+ }
|
||||
|
||||
return ret;
|
||||
}
|
||||
--- a/drivers/thermal/qcom/tsens.h
|
||||
+++ b/drivers/thermal/qcom/tsens.h
|
||||
@@ -493,6 +493,7 @@ enum regfield_ids {
|
||||
* struct tsens_features - Features supported by the IP
|
||||
* @ver_major: Major number of IP version
|
||||
* @crit_int: does the IP support critical interrupts?
|
||||
+ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
|
||||
* @adc: do the sensors only output adc code (instead of temperature)?
|
||||
* @srot_split: does the IP neatly splits the register space into SROT and TM,
|
||||
* with SROT only being available to secure boot firmware?
|
||||
@@ -502,6 +503,7 @@ enum regfield_ids {
|
||||
struct tsens_features {
|
||||
unsigned int ver_major;
|
||||
unsigned int crit_int:1;
|
||||
+ unsigned int combo_int:1;
|
||||
unsigned int adc:1;
|
||||
unsigned int srot_split:1;
|
||||
unsigned int has_watchdog:1;
|
||||
@@ -0,0 +1,101 @@
|
||||
From 7805365fee582056b32c69cf35aafbb94b14a8ca Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 19 Aug 2022 00:02:43 +0200
|
||||
Subject: [PATCH] thermal/drivers/tsens: Allow configuring min and max trips
|
||||
|
||||
IPQ8074 and IPQ6018 dont support negative trip temperatures and support
|
||||
up to 204 degrees C as the max trip temperature.
|
||||
|
||||
So, instead of always setting the -40 as min and 120 degrees C as max
|
||||
allow it to be configured as part of the features.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20220818220245.338396-3-robimarko@gmail.com
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
---
|
||||
drivers/thermal/qcom/tsens-8960.c | 2 ++
|
||||
drivers/thermal/qcom/tsens-v0_1.c | 2 ++
|
||||
drivers/thermal/qcom/tsens-v1.c | 2 ++
|
||||
drivers/thermal/qcom/tsens-v2.c | 2 ++
|
||||
drivers/thermal/qcom/tsens.c | 4 ++--
|
||||
drivers/thermal/qcom/tsens.h | 4 ++++
|
||||
6 files changed, 14 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/thermal/qcom/tsens-8960.c
|
||||
+++ b/drivers/thermal/qcom/tsens-8960.c
|
||||
@@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_
|
||||
.adc = 1,
|
||||
.srot_split = 0,
|
||||
.max_sensors = 11,
|
||||
+ .trip_min_temp = -40000,
|
||||
+ .trip_max_temp = 120000,
|
||||
};
|
||||
|
||||
struct tsens_plat_data data_8960 = {
|
||||
--- a/drivers/thermal/qcom/tsens-v0_1.c
|
||||
+++ b/drivers/thermal/qcom/tsens-v0_1.c
|
||||
@@ -553,6 +553,8 @@ static struct tsens_features tsens_v0_1_
|
||||
.adc = 1,
|
||||
.srot_split = 1,
|
||||
.max_sensors = 11,
|
||||
+ .trip_min_temp = -40000,
|
||||
+ .trip_max_temp = 120000,
|
||||
};
|
||||
|
||||
static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
|
||||
--- a/drivers/thermal/qcom/tsens-v1.c
|
||||
+++ b/drivers/thermal/qcom/tsens-v1.c
|
||||
@@ -277,6 +277,8 @@ static struct tsens_features tsens_v1_fe
|
||||
.adc = 1,
|
||||
.srot_split = 1,
|
||||
.max_sensors = 11,
|
||||
+ .trip_min_temp = -40000,
|
||||
+ .trip_max_temp = 120000,
|
||||
};
|
||||
|
||||
static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
|
||||
--- a/drivers/thermal/qcom/tsens-v2.c
|
||||
+++ b/drivers/thermal/qcom/tsens-v2.c
|
||||
@@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_fe
|
||||
.adc = 0,
|
||||
.srot_split = 1,
|
||||
.max_sensors = 16,
|
||||
+ .trip_min_temp = -40000,
|
||||
+ .trip_max_temp = 120000,
|
||||
};
|
||||
|
||||
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
|
||||
--- a/drivers/thermal/qcom/tsens.c
|
||||
+++ b/drivers/thermal/qcom/tsens.c
|
||||
@@ -573,8 +573,8 @@ static int tsens_set_trips(struct therma
|
||||
dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
|
||||
hw_id, __func__, low, high);
|
||||
|
||||
- cl_high = clamp_val(high, -40000, 120000);
|
||||
- cl_low = clamp_val(low, -40000, 120000);
|
||||
+ cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
|
||||
+ cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
|
||||
|
||||
high_val = tsens_mC_to_hw(s, cl_high);
|
||||
low_val = tsens_mC_to_hw(s, cl_low);
|
||||
--- a/drivers/thermal/qcom/tsens.h
|
||||
+++ b/drivers/thermal/qcom/tsens.h
|
||||
@@ -499,6 +499,8 @@ enum regfield_ids {
|
||||
* with SROT only being available to secure boot firmware?
|
||||
* @has_watchdog: does this IP support watchdog functionality?
|
||||
* @max_sensors: maximum sensors supported by this version of the IP
|
||||
+ * @trip_min_temp: minimum trip temperature supported by this version of the IP
|
||||
+ * @trip_max_temp: maximum trip temperature supported by this version of the IP
|
||||
*/
|
||||
struct tsens_features {
|
||||
unsigned int ver_major;
|
||||
@@ -508,6 +510,8 @@ struct tsens_features {
|
||||
unsigned int srot_split:1;
|
||||
unsigned int has_watchdog:1;
|
||||
unsigned int max_sensors;
|
||||
+ int trip_min_temp;
|
||||
+ int trip_max_temp;
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -0,0 +1,74 @@
|
||||
From 0164d794cbc58488a7321272e95958d10cf103a4 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 19 Aug 2022 00:02:44 +0200
|
||||
Subject: [PATCH] thermal/drivers/tsens: Add IPQ8074 support
|
||||
|
||||
Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP
|
||||
it only has one IRQ, that is used for up/low as well as critical.
|
||||
It also does not support negative trip temperatures.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20220818220245.338396-4-robimarko@gmail.com
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
---
|
||||
drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++
|
||||
drivers/thermal/qcom/tsens.c | 3 +++
|
||||
drivers/thermal/qcom/tsens.h | 2 +-
|
||||
3 files changed, 21 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/thermal/qcom/tsens-v2.c
|
||||
+++ b/drivers/thermal/qcom/tsens-v2.c
|
||||
@@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_fe
|
||||
.trip_max_temp = 120000,
|
||||
};
|
||||
|
||||
+static struct tsens_features ipq8074_feat = {
|
||||
+ .ver_major = VER_2_X,
|
||||
+ .crit_int = 1,
|
||||
+ .combo_int = 1,
|
||||
+ .adc = 0,
|
||||
+ .srot_split = 1,
|
||||
+ .max_sensors = 16,
|
||||
+ .trip_min_temp = 0,
|
||||
+ .trip_max_temp = 204000,
|
||||
+};
|
||||
+
|
||||
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
|
||||
/* ----- SROT ------ */
|
||||
/* VERSION */
|
||||
@@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = {
|
||||
.fields = tsens_v2_regfields,
|
||||
};
|
||||
|
||||
+struct tsens_plat_data data_ipq8074 = {
|
||||
+ .ops = &ops_generic_v2,
|
||||
+ .feat = &ipq8074_feat,
|
||||
+ .fields = tsens_v2_regfields,
|
||||
+};
|
||||
+
|
||||
/* Kept around for backward compatibility with old msm8996.dtsi */
|
||||
struct tsens_plat_data data_8996 = {
|
||||
.num_sensors = 13,
|
||||
--- a/drivers/thermal/qcom/tsens.c
|
||||
+++ b/drivers/thermal/qcom/tsens.c
|
||||
@@ -981,6 +981,9 @@ static const struct of_device_id tsens_t
|
||||
.compatible = "qcom,ipq8064-tsens",
|
||||
.data = &data_8960,
|
||||
}, {
|
||||
+ .compatible = "qcom,ipq8074-tsens",
|
||||
+ .data = &data_ipq8074,
|
||||
+ }, {
|
||||
.compatible = "qcom,mdm9607-tsens",
|
||||
.data = &data_9607,
|
||||
}, {
|
||||
--- a/drivers/thermal/qcom/tsens.h
|
||||
+++ b/drivers/thermal/qcom/tsens.h
|
||||
@@ -597,6 +597,6 @@ extern struct tsens_plat_data data_8916,
|
||||
extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
|
||||
|
||||
/* TSENS v2 targets */
|
||||
-extern struct tsens_plat_data data_8996, data_tsens_v2;
|
||||
+extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
|
||||
|
||||
#endif /* __QCOM_TSENS_H__ */
|
||||
@@ -0,0 +1,130 @@
|
||||
From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 19 Aug 2022 00:02:45 +0200
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
|
||||
|
||||
IPQ8074 has a tsens v2.3.0 peripheral which monitors
|
||||
temperatures around the various subsystems on the
|
||||
die.
|
||||
|
||||
So lets add the tsens and thermal zone nodes, passive
|
||||
CPU cooling will come in later patches after CPU frequency
|
||||
scaling is supported.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
|
||||
1 file changed, 96 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -274,6 +274,16 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ tsens: thermal-sensor@4a9000 {
|
||||
+ compatible = "qcom,ipq8074-tsens";
|
||||
+ reg = <0x4a9000 0x1000>, /* TM */
|
||||
+ <0x4a8000 0x1000>; /* SROT */
|
||||
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "combined";
|
||||
+ #qcom,sensors = <16>;
|
||||
+ #thermal-sensor-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
cryptobam: dma-controller@704000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x00704000 0x20000>;
|
||||
@@ -874,4 +884,90 @@
|
||||
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
+
|
||||
+ thermal-zones {
|
||||
+ nss-top-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 4>;
|
||||
+ };
|
||||
+
|
||||
+ nss0-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 5>;
|
||||
+ };
|
||||
+
|
||||
+ nss1-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 6>;
|
||||
+ };
|
||||
+
|
||||
+ wcss-phya0-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 7>;
|
||||
+ };
|
||||
+
|
||||
+ wcss-phya1-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 8>;
|
||||
+ };
|
||||
+
|
||||
+ cpu0_thermal: cpu0-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 9>;
|
||||
+ };
|
||||
+
|
||||
+ cpu1_thermal: cpu1-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 10>;
|
||||
+ };
|
||||
+
|
||||
+ cpu2_thermal: cpu2-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 11>;
|
||||
+ };
|
||||
+
|
||||
+ cpu3_thermal: cpu3-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 12>;
|
||||
+ };
|
||||
+
|
||||
+ cluster_thermal: cluster-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 13>;
|
||||
+ };
|
||||
+
|
||||
+ wcss-phyb0-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 14>;
|
||||
+ };
|
||||
+
|
||||
+ wcss-phyb1-thermal {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsens 15>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
@@ -0,0 +1,29 @@
|
||||
From 0df592a0a1a3fff9133977192677aa915afc174f Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 19 Aug 2022 00:08:49 +0200
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: add clocks to APCS
|
||||
|
||||
APCS now has support for providing the APSS clocks as the child device
|
||||
for IPQ8074.
|
||||
|
||||
So, add the A53 PLL and XO clocks in order to use APCS as the CPU
|
||||
clocksource for APSS scaling.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -680,6 +680,8 @@
|
||||
apcs_glb: mailbox@b111000 {
|
||||
compatible = "qcom,ipq8074-apcs-apps-global";
|
||||
reg = <0x0b111000 0x1000>;
|
||||
+ clocks = <&a53pll>, <&xo>;
|
||||
+ clock-names = "pll", "xo";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#mbox-cells = <1>;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,59 @@
|
||||
From 813ba3e427671ba3ff35c825087b03f0ad91cf02 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Mon, 7 Nov 2022 14:28:59 +0100
|
||||
Subject: [PATCH] clk: qcom: reset: support resetting multiple bits
|
||||
|
||||
This patch adds the support for giving the complete bitmask
|
||||
in reset structure and reset operation will use this bitmask
|
||||
for all reset operations.
|
||||
|
||||
Currently, reset structure only takes a single bit for each reset
|
||||
and then calculates the bitmask by using the BIT() macro.
|
||||
|
||||
However, this is not sufficient anymore for newer SoC-s like IPQ8074,
|
||||
IPQ6018 and more, since their networking resets require multiple bits
|
||||
to be asserted in order to properly reset the HW block completely.
|
||||
|
||||
So, in order to allow asserting multiple bits add "bitmask" field to
|
||||
qcom_reset_map, and then use that bitmask value if its populated in the
|
||||
driver, if its not populated, then we just default to existing behaviour
|
||||
and calculate the bitmask on the fly.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20221107132901.489240-1-robimarko@gmail.com
|
||||
---
|
||||
drivers/clk/qcom/reset.c | 4 ++--
|
||||
drivers/clk/qcom/reset.h | 1 +
|
||||
2 files changed, 3 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/clk/qcom/reset.c
|
||||
+++ b/drivers/clk/qcom/reset.c
|
||||
@@ -30,7 +30,7 @@ qcom_reset_assert(struct reset_controlle
|
||||
|
||||
rst = to_qcom_reset_controller(rcdev);
|
||||
map = &rst->reset_map[id];
|
||||
- mask = BIT(map->bit);
|
||||
+ mask = map->bitmask ? map->bitmask : BIT(map->bit);
|
||||
|
||||
return regmap_update_bits(rst->regmap, map->reg, mask, mask);
|
||||
}
|
||||
@@ -44,7 +44,7 @@ qcom_reset_deassert(struct reset_control
|
||||
|
||||
rst = to_qcom_reset_controller(rcdev);
|
||||
map = &rst->reset_map[id];
|
||||
- mask = BIT(map->bit);
|
||||
+ mask = map->bitmask ? map->bitmask : BIT(map->bit);
|
||||
|
||||
return regmap_update_bits(rst->regmap, map->reg, mask, 0);
|
||||
}
|
||||
--- a/drivers/clk/qcom/reset.h
|
||||
+++ b/drivers/clk/qcom/reset.h
|
||||
@@ -12,6 +12,7 @@ struct qcom_reset_map {
|
||||
unsigned int reg;
|
||||
u8 bit;
|
||||
u8 udelay;
|
||||
+ u32 bitmask;
|
||||
};
|
||||
|
||||
struct regmap;
|
||||
@@ -0,0 +1,39 @@
|
||||
From e78a40eb24187a8b4f9b89e2181f674df39c2013 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Mon, 7 Nov 2022 14:29:00 +0100
|
||||
Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add missing networking
|
||||
resets
|
||||
|
||||
Add bindings for the missing networking resets found in IPQ8074 GCC.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20221107132901.489240-2-robimarko@gmail.com
|
||||
---
|
||||
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
||||
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
||||
@@ -367,6 +367,20 @@
|
||||
#define GCC_PCIE1_AHB_ARES 129
|
||||
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
|
||||
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
|
||||
+#define GCC_PPE_FULL_RESET 132
|
||||
+#define GCC_UNIPHY0_SOFT_RESET 133
|
||||
+#define GCC_UNIPHY0_XPCS_RESET 134
|
||||
+#define GCC_UNIPHY1_SOFT_RESET 135
|
||||
+#define GCC_UNIPHY1_XPCS_RESET 136
|
||||
+#define GCC_UNIPHY2_SOFT_RESET 137
|
||||
+#define GCC_UNIPHY2_XPCS_RESET 138
|
||||
+#define GCC_EDMA_HW_RESET 139
|
||||
+#define GCC_NSSPORT1_RESET 140
|
||||
+#define GCC_NSSPORT2_RESET 141
|
||||
+#define GCC_NSSPORT3_RESET 142
|
||||
+#define GCC_NSSPORT4_RESET 143
|
||||
+#define GCC_NSSPORT5_RESET 144
|
||||
+#define GCC_NSSPORT6_RESET 145
|
||||
|
||||
#define USB0_GDSC 0
|
||||
#define USB1_GDSC 1
|
||||
@@ -0,0 +1,41 @@
|
||||
From da76cb63d04dc22ed32123b8c1d084c006d67bfb Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Mon, 7 Nov 2022 14:29:01 +0100
|
||||
Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets
|
||||
|
||||
Downstream QCA 5.4 kernel defines networking resets which are not present
|
||||
in the mainline kernel but are required for the networking drivers.
|
||||
|
||||
So, port the downstream resets and avoid using magic values for mask,
|
||||
construct mask for resets which require multiple bits to be set/cleared.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq8074.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq8074.c
|
||||
@@ -4671,6 +4671,20 @@ static const struct qcom_reset_map gcc_i
|
||||
[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
|
||||
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
|
||||
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
|
||||
+ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
|
||||
+ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
|
||||
+ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
|
||||
+ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
|
||||
+ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
|
||||
+ [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
|
||||
+ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
|
||||
+ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
|
||||
+ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
|
||||
+ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
|
||||
+ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
|
||||
+ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
|
||||
+ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
|
||||
+ [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
|
||||
};
|
||||
|
||||
static struct gdsc *gcc_ipq8074_gdscs[] = {
|
||||
@@ -0,0 +1,152 @@
|
||||
From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Wed, 16 Nov 2022 22:46:55 +0100
|
||||
Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
|
||||
|
||||
It appears that having only .name populated in parent_data for clocks
|
||||
which are only globally searchable currently will not work as the clk core
|
||||
won't copy that name if there is no .fw_name present as well.
|
||||
|
||||
So, populate .fw_name for all parent clocks in parent_data.
|
||||
|
||||
Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
|
||||
|
||||
Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
|
||||
1 file changed, 26 insertions(+), 26 deletions(-)
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq8074.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq8074.c
|
||||
@@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
|
||||
- { .name = "pcie20_phy0_pipe_clk" },
|
||||
+ { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
};
|
||||
|
||||
@@ -733,7 +733,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
|
||||
- { .name = "pcie20_phy1_pipe_clk" },
|
||||
+ { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
};
|
||||
|
||||
@@ -1137,7 +1137,7 @@ static const struct freq_tbl ftbl_nss_no
|
||||
|
||||
static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
- { .name = "bias_pll_nss_noc_clk" },
|
||||
+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
|
||||
{ .hw = &gpll0.clkr.hw },
|
||||
{ .hw = &gpll2.clkr.hw },
|
||||
};
|
||||
@@ -1362,7 +1362,7 @@ static const struct freq_tbl ftbl_nss_pp
|
||||
|
||||
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
- { .name = "bias_pll_cc_clk" },
|
||||
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
|
||||
{ .hw = &gpll0.clkr.hw },
|
||||
{ .hw = &gpll4.clkr.hw },
|
||||
{ .hw = &nss_crypto_pll.clkr.hw },
|
||||
@@ -1413,10 +1413,10 @@ static const struct freq_tbl ftbl_nss_po
|
||||
|
||||
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
- { .name = "uniphy0_gcc_rx_clk" },
|
||||
- { .name = "uniphy0_gcc_tx_clk" },
|
||||
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
|
||||
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
|
||||
{ .hw = &ubi32_pll.clkr.hw },
|
||||
- { .name = "bias_pll_cc_clk" },
|
||||
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
|
||||
@@ -1465,10 +1465,10 @@ static const struct freq_tbl ftbl_nss_po
|
||||
|
||||
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
- { .name = "uniphy0_gcc_tx_clk" },
|
||||
- { .name = "uniphy0_gcc_rx_clk" },
|
||||
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
|
||||
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
|
||||
{ .hw = &ubi32_pll.clkr.hw },
|
||||
- { .name = "bias_pll_cc_clk" },
|
||||
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
|
||||
@@ -1696,12 +1696,12 @@ static const struct freq_tbl ftbl_nss_po
|
||||
|
||||
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
- { .name = "uniphy0_gcc_rx_clk" },
|
||||
- { .name = "uniphy0_gcc_tx_clk" },
|
||||
- { .name = "uniphy1_gcc_rx_clk" },
|
||||
- { .name = "uniphy1_gcc_tx_clk" },
|
||||
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
|
||||
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
|
||||
+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
|
||||
+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
|
||||
{ .hw = &ubi32_pll.clkr.hw },
|
||||
- { .name = "bias_pll_cc_clk" },
|
||||
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map
|
||||
@@ -1758,12 +1758,12 @@ static const struct freq_tbl ftbl_nss_po
|
||||
|
||||
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
- { .name = "uniphy0_gcc_tx_clk" },
|
||||
- { .name = "uniphy0_gcc_rx_clk" },
|
||||
- { .name = "uniphy1_gcc_tx_clk" },
|
||||
- { .name = "uniphy1_gcc_rx_clk" },
|
||||
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
|
||||
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
|
||||
+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
|
||||
+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
|
||||
{ .hw = &ubi32_pll.clkr.hw },
|
||||
- { .name = "bias_pll_cc_clk" },
|
||||
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map
|
||||
@@ -1820,10 +1820,10 @@ static const struct freq_tbl ftbl_nss_po
|
||||
|
||||
static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
- { .name = "uniphy2_gcc_rx_clk" },
|
||||
- { .name = "uniphy2_gcc_tx_clk" },
|
||||
+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
|
||||
+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
|
||||
{ .hw = &ubi32_pll.clkr.hw },
|
||||
- { .name = "bias_pll_cc_clk" },
|
||||
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
|
||||
@@ -1877,10 +1877,10 @@ static const struct freq_tbl ftbl_nss_po
|
||||
|
||||
static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
- { .name = "uniphy2_gcc_tx_clk" },
|
||||
- { .name = "uniphy2_gcc_rx_clk" },
|
||||
+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
|
||||
+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
|
||||
{ .hw = &ubi32_pll.clkr.hw },
|
||||
- { .name = "bias_pll_cc_clk" },
|
||||
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
|
||||
@@ -0,0 +1,36 @@
|
||||
From 9033c3c86ea0dd35bd2ab957317573b755967298 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Sun, 30 Oct 2022 18:57:03 +0100
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: pass XO and sleep clocks to GCC
|
||||
|
||||
Pass XO and sleep clocks to the GCC controller so it does not have to
|
||||
find them by matching globaly by name.
|
||||
|
||||
If not passed directly, driver maintains backwards compatibility by then
|
||||
falling back to global lookup.
|
||||
|
||||
Since we are here, set cell numbers in decimal instead of hex.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -361,9 +361,11 @@
|
||||
gcc: gcc@1800000 {
|
||||
compatible = "qcom,gcc-ipq8074";
|
||||
reg = <0x01800000 0x80000>;
|
||||
- #clock-cells = <0x1>;
|
||||
+ clocks = <&xo>, <&sleep_clk>;
|
||||
+ clock-names = "xo", "sleep_clk";
|
||||
+ #clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
- #reset-cells = <0x1>;
|
||||
+ #reset-cells = <1>;
|
||||
};
|
||||
|
||||
tcsr_mutex: hwlock@1905000 {
|
||||
@@ -0,0 +1,149 @@
|
||||
From fb76b808f8628215afebaf0f8af0bde635302590 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 19 Aug 2022 00:18:14 +0200
|
||||
Subject: [PATCH] arm64: dts: qcom: add PMP8074 DTSI
|
||||
|
||||
PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is
|
||||
controlled via SPMI.
|
||||
|
||||
Add DTSI for it providing GPIO, regulator, RTC and VADC support.
|
||||
|
||||
RTC is disabled by default as there is no built-in battery so it will
|
||||
loose time unless board vendor added a battery, so make it optional.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++
|
||||
1 file changed, 125 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
|
||||
@@ -0,0 +1,125 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
|
||||
+
|
||||
+#include <dt-bindings/spmi/spmi.h>
|
||||
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
|
||||
+
|
||||
+&spmi_bus {
|
||||
+ pmic@0 {
|
||||
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
|
||||
+ reg = <0x0 SPMI_USID>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ pmp8074_adc: adc@3100 {
|
||||
+ compatible = "qcom,spmi-adc-rev2";
|
||||
+ reg = <0x3100>;
|
||||
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ #io-channel-cells = <1>;
|
||||
+
|
||||
+ ref-gnd@0 {
|
||||
+ reg = <ADC5_REF_GND>;
|
||||
+ qcom,pre-scaling = <1 1>;
|
||||
+ };
|
||||
+
|
||||
+ vref-1p25@1 {
|
||||
+ reg = <ADC5_1P25VREF>;
|
||||
+ qcom,pre-scaling = <1 1>;
|
||||
+ };
|
||||
+
|
||||
+ vref-vadc@2 {
|
||||
+ reg = <ADC5_VREF_VADC>;
|
||||
+ qcom,pre-scaling = <1 1>;
|
||||
+ };
|
||||
+
|
||||
+ pmic_die: die-temp@6 {
|
||||
+ reg = <ADC5_DIE_TEMP>;
|
||||
+ qcom,pre-scaling = <1 1>;
|
||||
+ };
|
||||
+
|
||||
+ xo_therm: xo-temp@76 {
|
||||
+ reg = <ADC5_XO_THERM_100K_PU>;
|
||||
+ qcom,ratiometric;
|
||||
+ qcom,hw-settle-time = <200>;
|
||||
+ qcom,pre-scaling = <1 1>;
|
||||
+ };
|
||||
+
|
||||
+ pa_therm1: thermistor1@77 {
|
||||
+ reg = <ADC5_AMUX_THM1_100K_PU>;
|
||||
+ qcom,ratiometric;
|
||||
+ qcom,hw-settle-time = <200>;
|
||||
+ qcom,pre-scaling = <1 1>;
|
||||
+ };
|
||||
+
|
||||
+ pa_therm2: thermistor2@78 {
|
||||
+ reg = <ADC5_AMUX_THM2_100K_PU>;
|
||||
+ qcom,ratiometric;
|
||||
+ qcom,hw-settle-time = <200>;
|
||||
+ qcom,pre-scaling = <1 1>;
|
||||
+ };
|
||||
+
|
||||
+ pa_therm3: thermistor3@79 {
|
||||
+ reg = <ADC5_AMUX_THM3_100K_PU>;
|
||||
+ qcom,ratiometric;
|
||||
+ qcom,hw-settle-time = <200>;
|
||||
+ qcom,pre-scaling = <1 1>;
|
||||
+ };
|
||||
+
|
||||
+ vph-pwr@131 {
|
||||
+ reg = <ADC5_VPH_PWR>;
|
||||
+ qcom,pre-scaling = <1 3>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmp8074_rtc: rtc@6000 {
|
||||
+ compatible = "qcom,pm8941-rtc";
|
||||
+ reg = <0x6000>;
|
||||
+ reg-names = "rtc", "alarm";
|
||||
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
|
||||
+ allow-set-time;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pmp8074_gpios: gpio@c000 {
|
||||
+ compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
|
||||
+ reg = <0xc000>;
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ gpio-ranges = <&pmp8074_gpios 0 0 12>;
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic@1 {
|
||||
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
|
||||
+ reg = <0x1 SPMI_USID>;
|
||||
+
|
||||
+ regulators {
|
||||
+ compatible = "qcom,pmp8074-regulators";
|
||||
+
|
||||
+ s3: s3 {
|
||||
+ regulator-name = "vdd_s3";
|
||||
+ regulator-min-microvolt = <592000>;
|
||||
+ regulator-max-microvolt = <1064000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+ s4: s4 {
|
||||
+ regulator-name = "vdd_s4";
|
||||
+ regulator-min-microvolt = <712000>;
|
||||
+ regulator-max-microvolt = <992000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+ l11: l11 {
|
||||
+ regulator-name = "l11";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@@ -0,0 +1,37 @@
|
||||
From 2c394cfc1779886048feca7dc7f4075da5f6328c Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 19 Aug 2022 00:18:15 +0200
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply
|
||||
|
||||
Since now we have control over the PMP8074 PMIC providing various system
|
||||
voltages including L11 which provides the SDIO/eMMC I/O voltage set it as
|
||||
the SDHCI VQMMC supply.
|
||||
|
||||
This allows SDHCI controller to switch to 1.8V I/O mode and support high
|
||||
speed modes like HS200 and HS400.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
||||
@@ -3,6 +3,7 @@
|
||||
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
#include "ipq8074.dtsi"
|
||||
+#include "pmp8074.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
|
||||
@@ -84,6 +85,7 @@
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
+ vqmmc-supply = <&l11>;
|
||||
};
|
||||
|
||||
&qusb_phy_0 {
|
||||
@@ -0,0 +1,42 @@
|
||||
From 82ceb86227b1fc15c76d5fc691b2bf425f1a63b3 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Mon, 7 Nov 2022 10:29:30 +0100
|
||||
Subject: [PATCH] arm64: dts: qcom: hk01: use GPIO flags for tlmm
|
||||
|
||||
Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of
|
||||
harcoding the cell value.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20221107092930.33325-3-robimarko@gmail.com
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 5 +++--
|
||||
1 file changed, 3 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
||||
@@ -4,6 +4,7 @@
|
||||
*/
|
||||
#include "ipq8074.dtsi"
|
||||
#include "pmp8074.dtsi"
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
|
||||
@@ -52,12 +53,12 @@
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
- perst-gpios = <&tlmm 61 0x1>;
|
||||
+ perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
- perst-gpios = <&tlmm 58 0x1>;
|
||||
+ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie_qmp0 {
|
||||
@@ -0,0 +1,82 @@
|
||||
From 1b1c1423ca3e740984aa883512a72c4ea08fbe28 Mon Sep 17 00:00:00 2001
|
||||
From: Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
Date: Mon, 7 Nov 2022 15:55:17 +0100
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074-*: Fix up comments
|
||||
|
||||
Make sure all multiline C-style commends begin with just '/*' with
|
||||
the comment text starting on a new line.
|
||||
|
||||
Also, fix up some whitespace within comments.
|
||||
|
||||
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20221107145522.6706-8-konrad.dybcio@linaro.org
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 3 ++-
|
||||
arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts | 3 ++-
|
||||
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts | 3 ++-
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++------
|
||||
4 files changed, 12 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
|
||||
@@ -1,6 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/dts-v1/;
|
||||
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
+/*
|
||||
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
#include "ipq8074.dtsi"
|
||||
#include "pmp8074.dtsi"
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
|
||||
@@ -1,5 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
|
||||
+/*
|
||||
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
|
||||
@@ -1,6 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/dts-v1/;
|
||||
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
|
||||
+/*
|
||||
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
#include "ipq8074-hk10.dtsi"
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -129,10 +129,10 @@
|
||||
status = "disabled";
|
||||
|
||||
usb1_ssphy: phy@58200 {
|
||||
- reg = <0x00058200 0x130>, /* Tx */
|
||||
+ reg = <0x00058200 0x130>, /* Tx */
|
||||
<0x00058400 0x200>, /* Rx */
|
||||
- <0x00058800 0x1f8>, /* PCS */
|
||||
- <0x00058600 0x044>; /* PCS misc*/
|
||||
+ <0x00058800 0x1f8>, /* PCS */
|
||||
+ <0x00058600 0x044>; /* PCS misc */
|
||||
#phy-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&gcc GCC_USB1_PIPE_CLK>;
|
||||
@@ -172,10 +172,10 @@
|
||||
status = "disabled";
|
||||
|
||||
usb0_ssphy: phy@78200 {
|
||||
- reg = <0x00078200 0x130>, /* Tx */
|
||||
+ reg = <0x00078200 0x130>, /* Tx */
|
||||
<0x00078400 0x200>, /* Rx */
|
||||
- <0x00078800 0x1f8>, /* PCS */
|
||||
- <0x00078600 0x044>; /* PCS misc*/
|
||||
+ <0x00078800 0x1f8>, /* PCS */
|
||||
+ <0x00078600 0x044>; /* PCS misc */
|
||||
#phy-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&gcc GCC_USB0_PIPE_CLK>;
|
||||
@@ -0,0 +1,60 @@
|
||||
From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
|
||||
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Date: Tue, 8 Nov 2022 15:23:57 +0100
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
|
||||
DT schema
|
||||
|
||||
DT schema expects TLMM pin configuration nodes to be named with
|
||||
'-state' suffix and their optional children with '-pins' suffix.
|
||||
|
||||
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -318,35 +318,35 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x2>;
|
||||
|
||||
- serial_4_pins: serial4-pinmux {
|
||||
+ serial_4_pins: serial4-state {
|
||||
pins = "gpio23", "gpio24";
|
||||
function = "blsp4_uart1";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
- i2c_0_pins: i2c-0-pinmux {
|
||||
+ i2c_0_pins: i2c-0-state {
|
||||
pins = "gpio42", "gpio43";
|
||||
function = "blsp1_i2c";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
- spi_0_pins: spi-0-pins {
|
||||
+ spi_0_pins: spi-0-state {
|
||||
pins = "gpio38", "gpio39", "gpio40", "gpio41";
|
||||
function = "blsp0_spi";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
- hsuart_pins: hsuart-pins {
|
||||
+ hsuart_pins: hsuart-state {
|
||||
pins = "gpio46", "gpio47", "gpio48", "gpio49";
|
||||
function = "blsp2_uart";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
- qpic_pins: qpic-pins {
|
||||
+ qpic_pins: qpic-state {
|
||||
pins = "gpio1", "gpio3", "gpio4",
|
||||
"gpio5", "gpio6", "gpio7",
|
||||
"gpio8", "gpio10", "gpio11",
|
||||
@@ -0,0 +1,24 @@
|
||||
From a4748d2850783d36f77ccf2b5fcc86ccf1800ef1 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Wed, 16 Nov 2022 22:48:36 +0100
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed
|
||||
|
||||
Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
|
||||
generation limit.
|
||||
This allows the generic DWC code to configure the link speed correctly.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -766,6 +766,7 @@
|
||||
linux,pci-domain = <1>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
+ max-link-speed = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
@@ -0,0 +1,26 @@
|
||||
From f356132229b18ceef5d5ef9103bbaa9bdeb84c8d Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 13 Jan 2023 17:44:47 +0100
|
||||
Subject: [PATCH] PCI: qcom: Add IPQ8074 Gen3 port support
|
||||
|
||||
IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
|
||||
Add compatible for Gen3 port which uses the same controller as IPQ6018.
|
||||
|
||||
Link: https://lore.kernel.org/r/20230113164449.906002-7-robimarko@gmail.com
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
|
||||
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
||||
---
|
||||
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/pci/controller/dwc/pcie-qcom.c
|
||||
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
|
||||
@@ -1745,6 +1745,7 @@ static const struct of_device_id qcom_pc
|
||||
{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
|
||||
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
|
||||
{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
|
||||
+ { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
|
||||
{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
|
||||
{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
|
||||
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
|
||||
@@ -0,0 +1,38 @@
|
||||
From 614d31c231c7707322b643f409eeb7e28adc7f8c Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Sun, 8 Jan 2023 13:36:28 +0100
|
||||
Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for usb3phy-s
|
||||
|
||||
Having only .name populated in parent_data for clocks which are only
|
||||
globally searchable currently will not work as the clk core won't copy
|
||||
that name if there is no .fw_name present as well.
|
||||
|
||||
So, populate .fw_name for usb3phy clocks in parent_data as they were
|
||||
missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
|
||||
|
||||
Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq8074.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq8074.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq8074.c
|
||||
@@ -934,7 +934,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
|
||||
- { .name = "usb3phy_0_cc_pipe_clk" },
|
||||
+ { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
};
|
||||
|
||||
@@ -1002,7 +1002,7 @@ static struct clk_rcg2 usb1_mock_utmi_cl
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
|
||||
- { .name = "usb3phy_1_cc_pipe_clk" },
|
||||
+ { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
|
||||
{ .fw_name = "xo", .name = "xo" },
|
||||
};
|
||||
|
||||
@@ -0,0 +1,77 @@
|
||||
From b8295c6eb276b60f7b75c53a9703ca8fee01eba2 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Date: Fri, 26 May 2023 13:09:17 +0200
|
||||
Subject: [PATCH] soc: qcom: mdt_loader: Fix unconditional call to
|
||||
scm_pas_mem_setup
|
||||
|
||||
Commit ebeb20a9cd3f ("soc: qcom: mdt_loader: Always invoke PAS
|
||||
mem_setup") dropped the relocate check and made pas_mem_setup run
|
||||
unconditionally. The code was later moved with commit f4e526ff7e38
|
||||
("soc: qcom: mdt_loader: Extract PAS operations") to
|
||||
qcom_mdt_pas_init() effectively losing track of what was actually
|
||||
done.
|
||||
|
||||
The assumption that PAS mem_setup can be done anytime was effectively
|
||||
wrong, with no good reason and this caused regression on some SoC
|
||||
that use remoteproc to bringup ath11k. One example is IPQ8074 SoC that
|
||||
effectively broke resulting in remoteproc silently die and ath11k not
|
||||
working.
|
||||
|
||||
On this SoC FW relocate is not enabled and PAS mem_setup was correctly
|
||||
skipped in previous kernel version resulting in correct bringup and
|
||||
function of remoteproc and ath11k.
|
||||
|
||||
To fix the regression, reintroduce the relocate check in
|
||||
qcom_mdt_pas_init() and correctly skip PAS mem_setup where relocate is
|
||||
not enabled.
|
||||
|
||||
Fixes: ebeb20a9cd3f ("soc: qcom: mdt_loader: Always invoke PAS mem_setup")
|
||||
Reported-by: Robert Marko <robimarko@gmail.com>
|
||||
Tested-by: Robert Marko <robimarko@gmail.com>
|
||||
Co-developed-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Cc: stable@vger.kernel.org
|
||||
---
|
||||
drivers/soc/qcom/mdt_loader.c | 16 +++++++++++-----
|
||||
1 file changed, 11 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/soc/qcom/mdt_loader.c
|
||||
+++ b/drivers/soc/qcom/mdt_loader.c
|
||||
@@ -210,6 +210,7 @@ int qcom_mdt_pas_init(struct device *dev
|
||||
const struct elf32_hdr *ehdr;
|
||||
phys_addr_t min_addr = PHYS_ADDR_MAX;
|
||||
phys_addr_t max_addr = 0;
|
||||
+ bool relocate = false;
|
||||
size_t metadata_len;
|
||||
void *metadata;
|
||||
int ret;
|
||||
@@ -224,6 +225,9 @@ int qcom_mdt_pas_init(struct device *dev
|
||||
if (!mdt_phdr_valid(phdr))
|
||||
continue;
|
||||
|
||||
+ if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
|
||||
+ relocate = true;
|
||||
+
|
||||
if (phdr->p_paddr < min_addr)
|
||||
min_addr = phdr->p_paddr;
|
||||
|
||||
@@ -246,11 +250,13 @@ int qcom_mdt_pas_init(struct device *dev
|
||||
goto out;
|
||||
}
|
||||
|
||||
- ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr);
|
||||
- if (ret) {
|
||||
- /* Unable to set up relocation */
|
||||
- dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name);
|
||||
- goto out;
|
||||
+ if (relocate) {
|
||||
+ ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr);
|
||||
+ if (ret) {
|
||||
+ /* Unable to set up relocation */
|
||||
+ dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name);
|
||||
+ goto out;
|
||||
+ }
|
||||
}
|
||||
|
||||
out:
|
||||
@@ -0,0 +1,203 @@
|
||||
From 032be4f49dda786fea9e1501212f6cd09a7ded96 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Date: Thu, 3 Nov 2022 14:49:43 +0100
|
||||
Subject: [PATCH] clk: qcom: clk-rcg2: introduce support for multiple conf for
|
||||
same freq
|
||||
|
||||
Some RCG frequency can be reached by multiple configuration.
|
||||
|
||||
We currently declare multiple configuration for the same frequency but
|
||||
that is not supported and always the first configuration will be taken.
|
||||
|
||||
These multiple configuration are needed as based on the current parent
|
||||
configuration, it may be needed to use a different configuration to
|
||||
reach the same frequency.
|
||||
|
||||
To handle this introduce 2 new macro, FM and C.
|
||||
|
||||
- FM is used to declare an empty freq_tbl with just the frequency and an
|
||||
array of confs to insert all the config for the provided frequency.
|
||||
|
||||
- C is used to declare a fre_conf where src, pre_div, m and n are
|
||||
provided.
|
||||
|
||||
The driver is changed to handle this special freq_tbl and select the
|
||||
correct config by calculating the final rate and deciding based on the
|
||||
one that is less different than the requested one.
|
||||
|
||||
Tested-by: Robert Marko <robimarko@gmail.com>
|
||||
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
||||
---
|
||||
drivers/clk/qcom/clk-rcg.h | 14 ++++++-
|
||||
drivers/clk/qcom/clk-rcg2.c | 84 +++++++++++++++++++++++++++++++++----
|
||||
2 files changed, 88 insertions(+), 10 deletions(-)
|
||||
|
||||
--- a/drivers/clk/qcom/clk-rcg.h
|
||||
+++ b/drivers/clk/qcom/clk-rcg.h
|
||||
@@ -7,7 +7,17 @@
|
||||
#include <linux/clk-provider.h>
|
||||
#include "clk-regmap.h"
|
||||
|
||||
-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
|
||||
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n), 0, NULL }
|
||||
+
|
||||
+#define FM(_f, _confs) { .freq = (_f), .confs_num = ARRAY_SIZE(_confs), .confs = (_confs) }
|
||||
+#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) }
|
||||
+
|
||||
+struct freq_conf {
|
||||
+ u8 src;
|
||||
+ u8 pre_div;
|
||||
+ u16 m;
|
||||
+ u16 n;
|
||||
+};
|
||||
|
||||
struct freq_tbl {
|
||||
unsigned long freq;
|
||||
@@ -15,6 +25,8 @@ struct freq_tbl {
|
||||
u8 pre_div;
|
||||
u16 m;
|
||||
u16 n;
|
||||
+ int confs_num;
|
||||
+ const struct freq_conf *confs;
|
||||
};
|
||||
|
||||
/**
|
||||
--- a/drivers/clk/qcom/clk-rcg2.c
|
||||
+++ b/drivers/clk/qcom/clk-rcg2.c
|
||||
@@ -209,11 +209,60 @@ clk_rcg2_recalc_rate(struct clk_hw *hw,
|
||||
return __clk_rcg2_recalc_rate(hw, parent_rate, cfg);
|
||||
}
|
||||
|
||||
+static void
|
||||
+clk_rcg2_select_conf(struct clk_hw *hw, struct freq_tbl *f_tbl,
|
||||
+ const struct freq_tbl *f, unsigned long req_rate)
|
||||
+{
|
||||
+ unsigned long best_rate = 0, parent_rate, rate;
|
||||
+ const struct freq_conf *conf, *best_conf;
|
||||
+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
+ struct clk_hw *p;
|
||||
+ int index, i;
|
||||
+
|
||||
+ /* Search in each provided config the one that is near the wanted rate */
|
||||
+ for (i = 0, conf = f->confs; i < f->confs_num; i++, conf++) {
|
||||
+ index = qcom_find_src_index(hw, rcg->parent_map, conf->src);
|
||||
+ if (index < 0)
|
||||
+ continue;
|
||||
+
|
||||
+ p = clk_hw_get_parent_by_index(hw, index);
|
||||
+ if (!p)
|
||||
+ continue;
|
||||
+
|
||||
+ parent_rate = clk_hw_get_rate(p);
|
||||
+ rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
|
||||
+
|
||||
+ if (rate == req_rate) {
|
||||
+ best_conf = conf;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ if (abs(req_rate - rate) < abs(best_rate - rate)) {
|
||||
+ best_rate = rate;
|
||||
+ best_conf = conf;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * Very unlikely.
|
||||
+ * Force the first conf if we can't find a correct config.
|
||||
+ */
|
||||
+ if (unlikely(i == f->confs_num))
|
||||
+ best_conf = f->confs;
|
||||
+
|
||||
+ /* Apply the config */
|
||||
+ f_tbl->src = best_conf->src;
|
||||
+ f_tbl->pre_div = best_conf->pre_div;
|
||||
+ f_tbl->m = best_conf->m;
|
||||
+ f_tbl->n = best_conf->n;
|
||||
+}
|
||||
+
|
||||
static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
|
||||
struct clk_rate_request *req,
|
||||
enum freq_policy policy)
|
||||
{
|
||||
unsigned long clk_flags, rate = req->rate;
|
||||
+ struct freq_tbl f_tbl;
|
||||
struct clk_hw *p;
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
int index;
|
||||
@@ -232,7 +281,15 @@ static int _freq_tbl_determine_rate(stru
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
- index = qcom_find_src_index(hw, rcg->parent_map, f->src);
|
||||
+ f_tbl = *f;
|
||||
+ /*
|
||||
+ * A single freq may be reached by multiple configuration.
|
||||
+ * Try to find the bast one if we have this kind of freq_table.
|
||||
+ */
|
||||
+ if (f->confs)
|
||||
+ clk_rcg2_select_conf(hw, &f_tbl, f, rate);
|
||||
+
|
||||
+ index = qcom_find_src_index(hw, rcg->parent_map, f_tbl.src);
|
||||
if (index < 0)
|
||||
return index;
|
||||
|
||||
@@ -242,18 +299,18 @@ static int _freq_tbl_determine_rate(stru
|
||||
return -EINVAL;
|
||||
|
||||
if (clk_flags & CLK_SET_RATE_PARENT) {
|
||||
- rate = f->freq;
|
||||
- if (f->pre_div) {
|
||||
+ rate = f_tbl.freq;
|
||||
+ if (f_tbl.pre_div) {
|
||||
if (!rate)
|
||||
rate = req->rate;
|
||||
rate /= 2;
|
||||
- rate *= f->pre_div + 1;
|
||||
+ rate *= f_tbl.pre_div + 1;
|
||||
}
|
||||
|
||||
- if (f->n) {
|
||||
+ if (f_tbl.n) {
|
||||
u64 tmp = rate;
|
||||
- tmp = tmp * f->n;
|
||||
- do_div(tmp, f->m);
|
||||
+ tmp = tmp * f_tbl.n;
|
||||
+ do_div(tmp, f_tbl.m);
|
||||
rate = tmp;
|
||||
}
|
||||
} else {
|
||||
@@ -261,7 +318,7 @@ static int _freq_tbl_determine_rate(stru
|
||||
}
|
||||
req->best_parent_hw = p;
|
||||
req->best_parent_rate = rate;
|
||||
- req->rate = f->freq;
|
||||
+ req->rate = f_tbl.freq;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -357,6 +414,7 @@ static int __clk_rcg2_set_rate(struct cl
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
const struct freq_tbl *f;
|
||||
+ struct freq_tbl f_tbl;
|
||||
|
||||
switch (policy) {
|
||||
case FLOOR:
|
||||
@@ -372,7 +430,15 @@ static int __clk_rcg2_set_rate(struct cl
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
- return clk_rcg2_configure(rcg, f);
|
||||
+ f_tbl = *f;
|
||||
+ /*
|
||||
+ * A single freq may be reached by multiple configuration.
|
||||
+ * Try to find the best one if we have this kind of freq_table.
|
||||
+ */
|
||||
+ if (f->confs)
|
||||
+ clk_rcg2_select_conf(hw, &f_tbl, f, rate);
|
||||
+
|
||||
+ return clk_rcg2_configure(rcg, &f_tbl);
|
||||
}
|
||||
|
||||
static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
@@ -0,0 +1,129 @@
|
||||
From f778553f296792f4d1e8b3552603ad6116ea3eb3 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Date: Thu, 3 Nov 2022 14:49:44 +0100
|
||||
Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
|
||||
conf
|
||||
|
||||
Rework nss_port5/6 to use the new multiple configuration implementation
|
||||
and correctly fix the clocks for these port under some corner case.
|
||||
|
||||
This is particularly relevant for device that have 2.5G or 10G port
|
||||
connected to port5 or port 6 on ipq8074. As the parent are shared
|
||||
across multiple port it may be required to select the correct
|
||||
configuration to accomplish the desired clock. Without this patch such
|
||||
port doesn't work in some specific ethernet speed as the clock will be
|
||||
set to the wrong frequency as we just select the first configuration for
|
||||
the related frequency instead of selecting the best one.
|
||||
|
||||
Tested-by: Robert Marko <robimarko@gmail.com> # ipq8074 Qnap QHora-301W
|
||||
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq8074.c | 64 +++++++++++++++++++++++++---------
|
||||
1 file changed, 48 insertions(+), 16 deletions(-)
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq8074.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq8074.c
|
||||
@@ -1682,13 +1682,21 @@ static struct clk_regmap_div nss_port4_t
|
||||
},
|
||||
};
|
||||
|
||||
+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
|
||||
+ C(P_UNIPHY1_RX, 12.5, 0, 0),
|
||||
+ C(P_UNIPHY0_RX, 5, 0, 0),
|
||||
+};
|
||||
+
|
||||
+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
|
||||
+ C(P_UNIPHY1_RX, 2.5, 0, 0),
|
||||
+ C(P_UNIPHY0_RX, 1, 0, 0),
|
||||
+};
|
||||
+
|
||||
static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
|
||||
- F(25000000, P_UNIPHY0_RX, 5, 0, 0),
|
||||
+ FM(25000000, ftbl_nss_port5_rx_clk_src_25),
|
||||
F(78125000, P_UNIPHY1_RX, 4, 0, 0),
|
||||
- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
|
||||
- F(125000000, P_UNIPHY0_RX, 1, 0, 0),
|
||||
+ FM(125000000, ftbl_nss_port5_rx_clk_src_125),
|
||||
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
|
||||
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
|
||||
{ }
|
||||
@@ -1744,13 +1752,21 @@ static struct clk_regmap_div nss_port5_r
|
||||
},
|
||||
};
|
||||
|
||||
+static struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
|
||||
+ C(P_UNIPHY1_TX, 12.5, 0, 0),
|
||||
+ C(P_UNIPHY0_TX, 5, 0, 0),
|
||||
+};
|
||||
+
|
||||
+static struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
|
||||
+ C(P_UNIPHY1_TX, 2.5, 0, 0),
|
||||
+ C(P_UNIPHY0_TX, 1, 0, 0),
|
||||
+};
|
||||
+
|
||||
static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
|
||||
- F(25000000, P_UNIPHY0_TX, 5, 0, 0),
|
||||
+ FM(25000000, ftbl_nss_port5_tx_clk_src_25),
|
||||
F(78125000, P_UNIPHY1_TX, 4, 0, 0),
|
||||
- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
|
||||
- F(125000000, P_UNIPHY0_TX, 1, 0, 0),
|
||||
+ FM(125000000, ftbl_nss_port5_tx_clk_src_125),
|
||||
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
|
||||
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
|
||||
{ }
|
||||
@@ -1806,13 +1822,21 @@ static struct clk_regmap_div nss_port5_t
|
||||
},
|
||||
};
|
||||
|
||||
+static struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
|
||||
+ C(P_UNIPHY2_RX, 5, 0, 0),
|
||||
+ C(P_UNIPHY2_RX, 12.5, 0, 0),
|
||||
+};
|
||||
+
|
||||
+static struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
|
||||
+ C(P_UNIPHY2_RX, 1, 0, 0),
|
||||
+ C(P_UNIPHY2_RX, 2.5, 0, 0),
|
||||
+};
|
||||
+
|
||||
static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
- F(25000000, P_UNIPHY2_RX, 5, 0, 0),
|
||||
- F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
|
||||
+ FM(25000000, ftbl_nss_port6_rx_clk_src_25),
|
||||
F(78125000, P_UNIPHY2_RX, 4, 0, 0),
|
||||
- F(125000000, P_UNIPHY2_RX, 1, 0, 0),
|
||||
- F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
|
||||
+ FM(125000000, ftbl_nss_port6_rx_clk_src_125),
|
||||
F(156250000, P_UNIPHY2_RX, 2, 0, 0),
|
||||
F(312500000, P_UNIPHY2_RX, 1, 0, 0),
|
||||
{ }
|
||||
@@ -1863,13 +1887,21 @@ static struct clk_regmap_div nss_port6_r
|
||||
},
|
||||
};
|
||||
|
||||
+static struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
|
||||
+ C(P_UNIPHY2_TX, 5, 0, 0),
|
||||
+ C(P_UNIPHY2_TX, 12.5, 0, 0),
|
||||
+};
|
||||
+
|
||||
+static struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
|
||||
+ C(P_UNIPHY2_TX, 1, 0, 0),
|
||||
+ C(P_UNIPHY2_TX, 2.5, 0, 0),
|
||||
+};
|
||||
+
|
||||
static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
- F(25000000, P_UNIPHY2_TX, 5, 0, 0),
|
||||
- F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
|
||||
+ FM(25000000, ftbl_nss_port6_tx_clk_src_25),
|
||||
F(78125000, P_UNIPHY2_TX, 4, 0, 0),
|
||||
- F(125000000, P_UNIPHY2_TX, 1, 0, 0),
|
||||
- F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
|
||||
+ FM(125000000, ftbl_nss_port6_tx_clk_src_125),
|
||||
F(156250000, P_UNIPHY2_TX, 2, 0, 0),
|
||||
F(312500000, P_UNIPHY2_TX, 1, 0, 0),
|
||||
{ }
|
||||
@@ -0,0 +1,70 @@
|
||||
From ad2d07f71739351eeea1d8a120c0918e2c4b265f Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Wed, 22 Dec 2021 12:23:34 +0100
|
||||
Subject: [PATCH] arm64: dts: ipq8074: add reserved memory nodes
|
||||
|
||||
IPQ8074 has multiple reserved memory ranges, if they are not defined
|
||||
then weird things tend to happen, board hangs and resets when PCI or
|
||||
WLAN is used etc.
|
||||
|
||||
So, to avoid all of that add the reserved memory nodes from the downstream
|
||||
5.4 kernel from QCA.
|
||||
This is their default layout meant for devices with 1GB of RAM, but
|
||||
devices with lower ammounts can override the Q6 node.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 35 +++++++++++++++++++++++++++
|
||||
1 file changed, 35 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -85,6 +85,26 @@
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
+ nss@40000000 {
|
||||
+ no-map;
|
||||
+ reg = <0x0 0x40000000 0x0 0x01000000>;
|
||||
+ };
|
||||
+
|
||||
+ tzapp_region: tzapp@4a400000 {
|
||||
+ no-map;
|
||||
+ reg = <0x0 0x4a400000 0x0 0x00200000>;
|
||||
+ };
|
||||
+
|
||||
+ uboot@4a600000 {
|
||||
+ no-map;
|
||||
+ reg = <0x0 0x4a600000 0x0 0x00400000>;
|
||||
+ };
|
||||
+
|
||||
+ sbl@4aa00000 {
|
||||
+ no-map;
|
||||
+ reg = <0x0 0x4aa00000 0x0 0x00100000>;
|
||||
+ };
|
||||
+
|
||||
smem@4ab00000 {
|
||||
compatible = "qcom,smem";
|
||||
reg = <0x0 0x4ab00000 0x0 0x00100000>;
|
||||
@@ -97,6 +117,21 @@
|
||||
no-map;
|
||||
reg = <0x0 0x4ac00000 0x0 0x00400000>;
|
||||
};
|
||||
+
|
||||
+ q6_region: wcnss@4b000000 {
|
||||
+ no-map;
|
||||
+ reg = <0x0 0x4b000000 0x0 0x05f00000>;
|
||||
+ };
|
||||
+
|
||||
+ q6_etr_region: q6_etr_dump@50f00000 {
|
||||
+ no-map;
|
||||
+ reg = <0x0 0x50f00000 0x0 0x00100000>;
|
||||
+ };
|
||||
+
|
||||
+ m3_dump_region: m3_dump@51000000 {
|
||||
+ no-map;
|
||||
+ reg = <0x0 0x51000000 0x0 0x100000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
firmware {
|
||||
@@ -0,0 +1,30 @@
|
||||
From 8a576b5bc9f0555d1d970cacabcaa24a3b74fa57 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Wed, 16 Nov 2022 22:15:01 +0100
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to
|
||||
GCC
|
||||
|
||||
Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to
|
||||
find them by matching globaly by name.
|
||||
|
||||
If not passed directly, driver maintains backwards compatibility by then
|
||||
falling back to global lookup.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -396,8 +396,8 @@
|
||||
gcc: gcc@1800000 {
|
||||
compatible = "qcom,gcc-ipq8074";
|
||||
reg = <0x01800000 0x80000>;
|
||||
- clocks = <&xo>, <&sleep_clk>;
|
||||
- clock-names = "xo", "sleep_clk";
|
||||
+ clocks = <&xo>, <&sleep_clk>, <&pcie_phy0>, <&pcie_phy1>;
|
||||
+ clock-names = "xo", "sleep_clk", "pcie0_pipe", "pcie1_pipe";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
@@ -0,0 +1,43 @@
|
||||
From fb1f6850be00d8dd8a54017be4c1336e224069ac Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Wed, 16 Nov 2022 22:26:25 +0100
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: use msi-parent for PCIe
|
||||
|
||||
Instead of hardcoding the IRQ, simply use msi-parent instead.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +++-----
|
||||
1 file changed, 3 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -699,7 +699,7 @@
|
||||
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
|
||||
ranges = <0 0xb00a000 0xffd>;
|
||||
|
||||
- v2m@0 {
|
||||
+ gic_v2m0: v2m@0 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xffd>;
|
||||
@@ -811,8 +811,7 @@
|
||||
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
|
||||
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
|
||||
|
||||
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- interrupt-names = "msi";
|
||||
+ msi-parent = <&gic_v2m0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 142
|
||||
@@ -873,8 +872,7 @@
|
||||
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
|
||||
<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
|
||||
|
||||
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- interrupt-names = "msi";
|
||||
+ msi-parent = <&gic_v2m0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 75
|
||||
@@ -0,0 +1,155 @@
|
||||
From 125681433c8e526356947acf572fe8ca8ad32291 Mon Sep 17 00:00:00 2001
|
||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Date: Sat, 30 Jan 2021 10:50:05 +0530
|
||||
Subject: [PATCH] remoteproc: qcom: Add PRNG proxy clock
|
||||
|
||||
PRNG clock is needed by the secure PIL, support for the same
|
||||
is added in subsequent patches.
|
||||
|
||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
||||
---
|
||||
drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
|
||||
1 file changed, 47 insertions(+), 18 deletions(-)
|
||||
|
||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
@@ -91,19 +91,6 @@ enum {
|
||||
WCSS_QCS404,
|
||||
};
|
||||
|
||||
-struct wcss_data {
|
||||
- const char *firmware_name;
|
||||
- unsigned int crash_reason_smem;
|
||||
- u32 version;
|
||||
- bool aon_reset_required;
|
||||
- bool wcss_q6_reset_required;
|
||||
- const char *ssr_name;
|
||||
- const char *sysmon_name;
|
||||
- int ssctl_id;
|
||||
- const struct rproc_ops *ops;
|
||||
- bool requires_force_stop;
|
||||
-};
|
||||
-
|
||||
struct q6v5_wcss {
|
||||
struct device *dev;
|
||||
|
||||
@@ -128,6 +115,7 @@ struct q6v5_wcss {
|
||||
struct clk *qdsp6ss_xo_cbcr;
|
||||
struct clk *qdsp6ss_core_gfmux;
|
||||
struct clk *lcc_bcr_sleep;
|
||||
+ struct clk *prng_clk;
|
||||
struct regulator *cx_supply;
|
||||
struct qcom_sysmon *sysmon;
|
||||
|
||||
@@ -151,6 +139,21 @@ struct q6v5_wcss {
|
||||
struct qcom_rproc_ssr ssr_subdev;
|
||||
};
|
||||
|
||||
+struct wcss_data {
|
||||
+ int (*init_clock)(struct q6v5_wcss *wcss);
|
||||
+ int (*init_regulator)(struct q6v5_wcss *wcss);
|
||||
+ const char *firmware_name;
|
||||
+ unsigned int crash_reason_smem;
|
||||
+ u32 version;
|
||||
+ bool aon_reset_required;
|
||||
+ bool wcss_q6_reset_required;
|
||||
+ const char *ssr_name;
|
||||
+ const char *sysmon_name;
|
||||
+ int ssctl_id;
|
||||
+ const struct rproc_ops *ops;
|
||||
+ bool requires_force_stop;
|
||||
+};
|
||||
+
|
||||
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
|
||||
{
|
||||
int ret;
|
||||
@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc
|
||||
struct q6v5_wcss *wcss = rproc->priv;
|
||||
int ret;
|
||||
|
||||
+ ret = clk_prepare_enable(wcss->prng_clk);
|
||||
+ if (ret) {
|
||||
+ dev_err(wcss->dev, "prng clock enable failed\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
qcom_q6v5_prepare(&wcss->q6v5);
|
||||
|
||||
/* Release Q6 and WCSS reset */
|
||||
@@ -733,6 +742,7 @@ static int q6v5_wcss_stop(struct rproc *
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ clk_disable_unprepare(wcss->prng_clk);
|
||||
qcom_q6v5_unprepare(&wcss->q6v5);
|
||||
|
||||
return 0;
|
||||
@@ -900,7 +910,21 @@ static int q6v5_alloc_memory_region(stru
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
|
||||
+static int ipq8074_init_clock(struct q6v5_wcss *wcss)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ wcss->prng_clk = devm_clk_get(wcss->dev, "prng");
|
||||
+ if (IS_ERR(wcss->prng_clk)) {
|
||||
+ ret = PTR_ERR(wcss->prng_clk);
|
||||
+ if (ret != -EPROBE_DEFER)
|
||||
+ dev_err(wcss->dev, "Failed to get prng clock\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qcs404_init_clock(struct q6v5_wcss *wcss)
|
||||
{
|
||||
int ret;
|
||||
|
||||
@@ -990,7 +1014,7 @@ static int q6v5_wcss_init_clock(struct q
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
|
||||
+static int qcs404_init_regulator(struct q6v5_wcss *wcss)
|
||||
{
|
||||
wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
|
||||
if (IS_ERR(wcss->cx_supply))
|
||||
@@ -1034,12 +1058,14 @@ static int q6v5_wcss_probe(struct platfo
|
||||
if (ret)
|
||||
goto free_rproc;
|
||||
|
||||
- if (wcss->version == WCSS_QCS404) {
|
||||
- ret = q6v5_wcss_init_clock(wcss);
|
||||
+ if (desc->init_clock) {
|
||||
+ ret = desc->init_clock(wcss);
|
||||
if (ret)
|
||||
goto free_rproc;
|
||||
+ }
|
||||
|
||||
- ret = q6v5_wcss_init_regulator(wcss);
|
||||
+ if (desc->init_regulator) {
|
||||
+ ret = desc->init_regulator(wcss);
|
||||
if (ret)
|
||||
goto free_rproc;
|
||||
}
|
||||
@@ -1087,6 +1113,7 @@ static int q6v5_wcss_remove(struct platf
|
||||
}
|
||||
|
||||
static const struct wcss_data wcss_ipq8074_res_init = {
|
||||
+ .init_clock = ipq8074_init_clock,
|
||||
.firmware_name = "IPQ8074/q6_fw.mdt",
|
||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
||||
.aon_reset_required = true,
|
||||
@@ -1096,6 +1123,8 @@ static const struct wcss_data wcss_ipq80
|
||||
};
|
||||
|
||||
static const struct wcss_data wcss_qcs404_res_init = {
|
||||
+ .init_clock = qcs404_init_clock,
|
||||
+ .init_regulator = qcs404_init_regulator,
|
||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
||||
.firmware_name = "wcnss.mdt",
|
||||
.version = WCSS_QCS404,
|
||||
@@ -0,0 +1,143 @@
|
||||
From 7358d42dfbdfdb5d4f1d0d4c2e5c2bb4143a29b0 Mon Sep 17 00:00:00 2001
|
||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Date: Sat, 30 Jan 2021 10:50:06 +0530
|
||||
Subject: [PATCH] remoteproc: qcom: Add secure PIL support
|
||||
|
||||
IPQ8074 uses secure PIL. Hence, adding the support for the same.
|
||||
|
||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
||||
---
|
||||
drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++--
|
||||
1 file changed, 40 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
@@ -18,6 +18,7 @@
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/soc/qcom/mdt_loader.h>
|
||||
+#include <linux/qcom_scm.h>
|
||||
#include "qcom_common.h"
|
||||
#include "qcom_pil_info.h"
|
||||
#include "qcom_q6v5.h"
|
||||
@@ -86,6 +87,9 @@
|
||||
#define TCSR_WCSS_CLK_ENABLE 0x14
|
||||
|
||||
#define MAX_HALT_REG 3
|
||||
+
|
||||
+#define WCNSS_PAS_ID 6
|
||||
+
|
||||
enum {
|
||||
WCSS_IPQ8074,
|
||||
WCSS_QCS404,
|
||||
@@ -134,6 +138,7 @@ struct q6v5_wcss {
|
||||
unsigned int crash_reason_smem;
|
||||
u32 version;
|
||||
bool requires_force_stop;
|
||||
+ bool need_mem_protection;
|
||||
|
||||
struct qcom_rproc_glink glink_subdev;
|
||||
struct qcom_rproc_ssr ssr_subdev;
|
||||
@@ -152,6 +157,7 @@ struct wcss_data {
|
||||
int ssctl_id;
|
||||
const struct rproc_ops *ops;
|
||||
bool requires_force_stop;
|
||||
+ bool need_mem_protection;
|
||||
};
|
||||
|
||||
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
|
||||
@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc
|
||||
|
||||
qcom_q6v5_prepare(&wcss->q6v5);
|
||||
|
||||
+ if (wcss->need_mem_protection) {
|
||||
+ ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
|
||||
+ if (ret) {
|
||||
+ dev_err(wcss->dev, "wcss_reset failed\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ goto wait_for_reset;
|
||||
+ }
|
||||
+
|
||||
/* Release Q6 and WCSS reset */
|
||||
ret = reset_control_deassert(wcss->wcss_reset);
|
||||
if (ret) {
|
||||
@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc
|
||||
if (ret)
|
||||
goto wcss_q6_reset;
|
||||
|
||||
+wait_for_reset:
|
||||
ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
|
||||
if (ret == -ETIMEDOUT)
|
||||
dev_err(wcss->dev, "start timed out\n");
|
||||
@@ -718,6 +734,15 @@ static int q6v5_wcss_stop(struct rproc *
|
||||
struct q6v5_wcss *wcss = rproc->priv;
|
||||
int ret;
|
||||
|
||||
+ if (wcss->need_mem_protection) {
|
||||
+ ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
|
||||
+ if (ret) {
|
||||
+ dev_err(wcss->dev, "not able to shutdown\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ goto pas_done;
|
||||
+ }
|
||||
+
|
||||
/* WCSS powerdown */
|
||||
if (wcss->requires_force_stop) {
|
||||
ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
|
||||
@@ -742,6 +767,7 @@ static int q6v5_wcss_stop(struct rproc *
|
||||
return ret;
|
||||
}
|
||||
|
||||
+pas_done:
|
||||
clk_disable_unprepare(wcss->prng_clk);
|
||||
qcom_q6v5_unprepare(&wcss->q6v5);
|
||||
|
||||
@@ -765,9 +791,15 @@ static int q6v5_wcss_load(struct rproc *
|
||||
struct q6v5_wcss *wcss = rproc->priv;
|
||||
int ret;
|
||||
|
||||
- ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
|
||||
- 0, wcss->mem_region, wcss->mem_phys,
|
||||
- wcss->mem_size, &wcss->mem_reloc);
|
||||
+ if (wcss->need_mem_protection)
|
||||
+ ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
|
||||
+ WCNSS_PAS_ID, wcss->mem_region,
|
||||
+ wcss->mem_phys, wcss->mem_size,
|
||||
+ &wcss->mem_reloc);
|
||||
+ else
|
||||
+ ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
|
||||
+ 0, wcss->mem_region, wcss->mem_phys,
|
||||
+ wcss->mem_size, &wcss->mem_reloc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@@ -1036,6 +1068,9 @@ static int q6v5_wcss_probe(struct platfo
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
+ if (desc->need_mem_protection && !qcom_scm_is_available())
|
||||
+ return -EPROBE_DEFER;
|
||||
+
|
||||
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
|
||||
desc->firmware_name, sizeof(*wcss));
|
||||
if (!rproc) {
|
||||
@@ -1049,6 +1084,7 @@ static int q6v5_wcss_probe(struct platfo
|
||||
|
||||
wcss->version = desc->version;
|
||||
wcss->requires_force_stop = desc->requires_force_stop;
|
||||
+ wcss->need_mem_protection = desc->need_mem_protection;
|
||||
|
||||
ret = q6v5_wcss_init_mmio(wcss, pdev);
|
||||
if (ret)
|
||||
@@ -1120,6 +1156,7 @@ static const struct wcss_data wcss_ipq80
|
||||
.wcss_q6_reset_required = true,
|
||||
.ops = &q6v5_wcss_ipq8074_ops,
|
||||
.requires_force_stop = true,
|
||||
+ .need_mem_protection = true,
|
||||
};
|
||||
|
||||
static const struct wcss_data wcss_qcs404_res_init = {
|
||||
@@ -0,0 +1,103 @@
|
||||
From b422c9d4f048b086ce83f44a7cfcddcce162897f Mon Sep 17 00:00:00 2001
|
||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Date: Sat, 30 Jan 2021 10:50:07 +0530
|
||||
Subject: [PATCH] remoteproc: qcom: Add support for split q6 + m3 wlan firmware
|
||||
|
||||
IPQ8074 supports split firmware for q6 and m3 as well.
|
||||
So add support for loading the m3 firmware before q6.
|
||||
Now the drivers works fine for both split and unified
|
||||
firmwares.
|
||||
|
||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
||||
---
|
||||
drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++----
|
||||
1 file changed, 29 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
@@ -139,6 +139,7 @@ struct q6v5_wcss {
|
||||
u32 version;
|
||||
bool requires_force_stop;
|
||||
bool need_mem_protection;
|
||||
+ const char *m3_firmware_name;
|
||||
|
||||
struct qcom_rproc_glink glink_subdev;
|
||||
struct qcom_rproc_ssr ssr_subdev;
|
||||
@@ -147,7 +148,8 @@ struct q6v5_wcss {
|
||||
struct wcss_data {
|
||||
int (*init_clock)(struct q6v5_wcss *wcss);
|
||||
int (*init_regulator)(struct q6v5_wcss *wcss);
|
||||
- const char *firmware_name;
|
||||
+ const char *q6_firmware_name;
|
||||
+ const char *m3_firmware_name;
|
||||
unsigned int crash_reason_smem;
|
||||
u32 version;
|
||||
bool aon_reset_required;
|
||||
@@ -789,8 +791,29 @@ static void *q6v5_wcss_da_to_va(struct r
|
||||
static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
|
||||
{
|
||||
struct q6v5_wcss *wcss = rproc->priv;
|
||||
+ const struct firmware *m3_fw;
|
||||
int ret;
|
||||
|
||||
+ if (wcss->m3_firmware_name) {
|
||||
+ ret = request_firmware(&m3_fw, wcss->m3_firmware_name,
|
||||
+ wcss->dev);
|
||||
+ if (ret)
|
||||
+ goto skip_m3;
|
||||
+
|
||||
+ ret = qcom_mdt_load_no_init(wcss->dev, m3_fw,
|
||||
+ wcss->m3_firmware_name, 0,
|
||||
+ wcss->mem_region, wcss->mem_phys,
|
||||
+ wcss->mem_size, &wcss->mem_reloc);
|
||||
+
|
||||
+ release_firmware(m3_fw);
|
||||
+
|
||||
+ if (ret) {
|
||||
+ dev_err(wcss->dev, "can't load m3_fw.bXX\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+skip_m3:
|
||||
if (wcss->need_mem_protection)
|
||||
ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
|
||||
WCNSS_PAS_ID, wcss->mem_region,
|
||||
@@ -1072,7 +1095,7 @@ static int q6v5_wcss_probe(struct platfo
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
|
||||
- desc->firmware_name, sizeof(*wcss));
|
||||
+ desc->q6_firmware_name, sizeof(*wcss));
|
||||
if (!rproc) {
|
||||
dev_err(&pdev->dev, "failed to allocate rproc\n");
|
||||
return -ENOMEM;
|
||||
@@ -1085,6 +1108,7 @@ static int q6v5_wcss_probe(struct platfo
|
||||
wcss->version = desc->version;
|
||||
wcss->requires_force_stop = desc->requires_force_stop;
|
||||
wcss->need_mem_protection = desc->need_mem_protection;
|
||||
+ wcss->m3_firmware_name = desc->m3_firmware_name;
|
||||
|
||||
ret = q6v5_wcss_init_mmio(wcss, pdev);
|
||||
if (ret)
|
||||
@@ -1150,7 +1174,8 @@ static int q6v5_wcss_remove(struct platf
|
||||
|
||||
static const struct wcss_data wcss_ipq8074_res_init = {
|
||||
.init_clock = ipq8074_init_clock,
|
||||
- .firmware_name = "IPQ8074/q6_fw.mdt",
|
||||
+ .q6_firmware_name = "IPQ8074/q6_fw.mdt",
|
||||
+ .m3_firmware_name = "IPQ8074/m3_fw.mdt",
|
||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
||||
.aon_reset_required = true,
|
||||
.wcss_q6_reset_required = true,
|
||||
@@ -1163,7 +1188,7 @@ static const struct wcss_data wcss_qcs40
|
||||
.init_clock = qcs404_init_clock,
|
||||
.init_regulator = qcs404_init_regulator,
|
||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
||||
- .firmware_name = "wcnss.mdt",
|
||||
+ .q6_firmware_name = "wcnss.mdt",
|
||||
.version = WCSS_QCS404,
|
||||
.aon_reset_required = false,
|
||||
.wcss_q6_reset_required = false,
|
||||
@@ -0,0 +1,24 @@
|
||||
From 3a8f67b4770c817b04794c9a02e3f88f85d86280 Mon Sep 17 00:00:00 2001
|
||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Date: Sat, 30 Jan 2021 10:50:08 +0530
|
||||
Subject: [PATCH] remoteproc: qcom: Add ssr subdevice identifier
|
||||
|
||||
Add name for ssr subdevice on IPQ8074 SoC.
|
||||
|
||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
||||
---
|
||||
drivers/remoteproc/qcom_q6v5_wcss.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
@@ -1179,6 +1179,7 @@ static const struct wcss_data wcss_ipq80
|
||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
||||
.aon_reset_required = true,
|
||||
.wcss_q6_reset_required = true,
|
||||
+ .ssr_name = "q6wcss",
|
||||
.ops = &q6v5_wcss_ipq8074_ops,
|
||||
.requires_force_stop = true,
|
||||
.need_mem_protection = true,
|
||||
@@ -0,0 +1,79 @@
|
||||
From 8c73af6e8d78c66cfef0f551b00d375ec0b67ff3 Mon Sep 17 00:00:00 2001
|
||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Date: Sat, 30 Jan 2021 10:50:09 +0530
|
||||
Subject: [PATCH] remoteproc: qcom: Update regmap offsets for halt register
|
||||
|
||||
Fixed issue in reading halt-regs parameter from device-tree.
|
||||
|
||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
---
|
||||
drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++--------
|
||||
1 file changed, 14 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
@@ -86,7 +86,7 @@
|
||||
#define TCSR_WCSS_CLK_MASK 0x1F
|
||||
#define TCSR_WCSS_CLK_ENABLE 0x14
|
||||
|
||||
-#define MAX_HALT_REG 3
|
||||
+#define MAX_HALT_REG 4
|
||||
|
||||
#define WCNSS_PAS_ID 6
|
||||
|
||||
@@ -154,6 +154,7 @@ struct wcss_data {
|
||||
u32 version;
|
||||
bool aon_reset_required;
|
||||
bool wcss_q6_reset_required;
|
||||
+ bool bcr_reset_required;
|
||||
const char *ssr_name;
|
||||
const char *sysmon_name;
|
||||
int ssctl_id;
|
||||
@@ -875,10 +876,13 @@ static int q6v5_wcss_init_reset(struct q
|
||||
}
|
||||
}
|
||||
|
||||
- wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset");
|
||||
- if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
|
||||
- dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
|
||||
- return PTR_ERR(wcss->wcss_q6_bcr_reset);
|
||||
+ if (desc->bcr_reset_required) {
|
||||
+ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev,
|
||||
+ "wcss_q6_bcr_reset");
|
||||
+ if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
|
||||
+ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
|
||||
+ return PTR_ERR(wcss->wcss_q6_bcr_reset);
|
||||
+ }
|
||||
}
|
||||
|
||||
return 0;
|
||||
@@ -929,9 +933,9 @@ static int q6v5_wcss_init_mmio(struct q6
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- wcss->halt_q6 = halt_reg[0];
|
||||
- wcss->halt_wcss = halt_reg[1];
|
||||
- wcss->halt_nc = halt_reg[2];
|
||||
+ wcss->halt_q6 = halt_reg[1];
|
||||
+ wcss->halt_wcss = halt_reg[2];
|
||||
+ wcss->halt_nc = halt_reg[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1179,6 +1183,7 @@ static const struct wcss_data wcss_ipq80
|
||||
.crash_reason_smem = WCSS_CRASH_REASON,
|
||||
.aon_reset_required = true,
|
||||
.wcss_q6_reset_required = true,
|
||||
+ .bcr_reset_required = false,
|
||||
.ssr_name = "q6wcss",
|
||||
.ops = &q6v5_wcss_ipq8074_ops,
|
||||
.requires_force_stop = true,
|
||||
@@ -1193,6 +1198,7 @@ static const struct wcss_data wcss_qcs40
|
||||
.version = WCSS_QCS404,
|
||||
.aon_reset_required = false,
|
||||
.wcss_q6_reset_required = false,
|
||||
+ .bcr_reset_required = true,
|
||||
.ssr_name = "mpss",
|
||||
.sysmon_name = "wcnss",
|
||||
.ssctl_id = 0x12,
|
||||
@@ -0,0 +1,26 @@
|
||||
From ff7c6533ed8c4de58ed6c8aab03ea59c03eb4f31 Mon Sep 17 00:00:00 2001
|
||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Date: Sat, 30 Jan 2021 10:50:10 +0530
|
||||
Subject: [PATCH] dt-bindings: clock: qcom: Add reset for WCSSAON
|
||||
|
||||
Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
|
||||
|
||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
||||
Acked-by: Rob Herring <robh@kernel.org>
|
||||
Acked-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
||||
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
||||
@@ -381,6 +381,7 @@
|
||||
#define GCC_NSSPORT4_RESET 143
|
||||
#define GCC_NSSPORT5_RESET 144
|
||||
#define GCC_NSSPORT6_RESET 145
|
||||
+#define GCC_WCSSAON_RESET 146
|
||||
|
||||
#define USB0_GDSC 0
|
||||
#define USB1_GDSC 1
|
||||
@@ -0,0 +1,25 @@
|
||||
From 43d9788f546d24df22d8ba3fcc2497d7ccc198f3 Mon Sep 17 00:00:00 2001
|
||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Date: Sat, 30 Jan 2021 10:50:11 +0530
|
||||
Subject: [PATCH] clk: qcom: Add WCSSAON reset
|
||||
|
||||
Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
|
||||
|
||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
||||
Acked-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq8074.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq8074.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq8074.c
|
||||
@@ -4717,6 +4717,7 @@ static const struct qcom_reset_map gcc_i
|
||||
[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
|
||||
[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
|
||||
[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
|
||||
+ [GCC_WCSSAON_RESET] = { 0x59010, 0 },
|
||||
};
|
||||
|
||||
static struct gdsc *gcc_ipq8074_gdscs[] = {
|
||||
@@ -0,0 +1,48 @@
|
||||
From 406a332fd1bcc4e18d73cce390f56272fe9111d7 Mon Sep 17 00:00:00 2001
|
||||
From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
|
||||
Date: Fri, 17 Apr 2020 16:37:10 +0530
|
||||
Subject: [PATCH] remoteproc: wcss: disable auto boot for IPQ8074
|
||||
|
||||
There is no need for remoteproc to boot automatically, ath11k will trigger
|
||||
booting when its probing.
|
||||
|
||||
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
|
||||
@@ -161,6 +161,7 @@ struct wcss_data {
|
||||
const struct rproc_ops *ops;
|
||||
bool requires_force_stop;
|
||||
bool need_mem_protection;
|
||||
+ bool need_auto_boot;
|
||||
};
|
||||
|
||||
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
|
||||
@@ -1150,6 +1151,7 @@ static int q6v5_wcss_probe(struct platfo
|
||||
desc->sysmon_name,
|
||||
desc->ssctl_id);
|
||||
|
||||
+ rproc->auto_boot = desc->need_auto_boot;
|
||||
ret = rproc_add(rproc);
|
||||
if (ret)
|
||||
goto free_rproc;
|
||||
@@ -1188,6 +1190,7 @@ static const struct wcss_data wcss_ipq80
|
||||
.ops = &q6v5_wcss_ipq8074_ops,
|
||||
.requires_force_stop = true,
|
||||
.need_mem_protection = true,
|
||||
+ .need_auto_boot = false,
|
||||
};
|
||||
|
||||
static const struct wcss_data wcss_qcs404_res_init = {
|
||||
@@ -1204,6 +1207,7 @@ static const struct wcss_data wcss_qcs40
|
||||
.ssctl_id = 0x12,
|
||||
.ops = &q6v5_wcss_qcs404_ops,
|
||||
.requires_force_stop = false,
|
||||
+ .need_auto_boot = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id q6v5_wcss_of_match[] = {
|
||||
@@ -0,0 +1,120 @@
|
||||
From 7388400b8bd42f71d040dbf2fdbdcb834fcc0ede Mon Sep 17 00:00:00 2001
|
||||
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Date: Sat, 30 Jan 2021 10:50:13 +0530
|
||||
Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
|
||||
|
||||
Enable remoteproc WCSS PIL driver with glink and ssr subdevices.
|
||||
Also enables smp2p and mailboxes required for IPC.
|
||||
|
||||
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++
|
||||
1 file changed, 81 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -140,6 +140,32 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ wcss: smp2p-wcss {
|
||||
+ compatible = "qcom,smp2p";
|
||||
+ qcom,smem = <435>, <428>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <0 322 1>;
|
||||
+
|
||||
+ mboxes = <&apcs_glb 9>;
|
||||
+
|
||||
+ qcom,local-pid = <0>;
|
||||
+ qcom,remote-pid = <1>;
|
||||
+
|
||||
+ wcss_smp2p_out: master-kernel {
|
||||
+ qcom,entry-name = "master-kernel";
|
||||
+ qcom,smp2p-feature-ssr-ack;
|
||||
+ #qcom,smem-state-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ wcss_smp2p_in: slave-kernel {
|
||||
+ qcom,entry-name = "slave-kernel";
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
soc: soc {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
@@ -409,6 +435,11 @@
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
+ tcsr_q6: syscon@1945000 {
|
||||
+ compatible = "syscon";
|
||||
+ reg = <0x01945000 0xe000>;
|
||||
+ };
|
||||
+
|
||||
spmi_bus: spmi@200f000 {
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
reg = <0x0200f000 0x001000>,
|
||||
@@ -913,6 +944,56 @@
|
||||
"axi_s_sticky";
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+ q6v5_wcss: q6v5_wcss@cd00000 {
|
||||
+ compatible = "qcom,ipq8074-wcss-pil";
|
||||
+ reg = <0x0cd00000 0x4040>,
|
||||
+ <0x004ab000 0x20>;
|
||||
+ reg-names = "qdsp6",
|
||||
+ "rmb";
|
||||
+ qca,auto-restart;
|
||||
+ qca,extended-intc;
|
||||
+ interrupts-extended = <&intc 0 325 1>,
|
||||
+ <&wcss_smp2p_in 0 0>,
|
||||
+ <&wcss_smp2p_in 1 0>,
|
||||
+ <&wcss_smp2p_in 2 0>,
|
||||
+ <&wcss_smp2p_in 3 0>;
|
||||
+ interrupt-names = "wdog",
|
||||
+ "fatal",
|
||||
+ "ready",
|
||||
+ "handover",
|
||||
+ "stop-ack";
|
||||
+
|
||||
+ resets = <&gcc GCC_WCSSAON_RESET>,
|
||||
+ <&gcc GCC_WCSS_BCR>,
|
||||
+ <&gcc GCC_WCSS_Q6_BCR>;
|
||||
+
|
||||
+ reset-names = "wcss_aon_reset",
|
||||
+ "wcss_reset",
|
||||
+ "wcss_q6_reset";
|
||||
+
|
||||
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
||||
+ clock-names = "prng";
|
||||
+
|
||||
+ qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
|
||||
+
|
||||
+ qcom,smem-states = <&wcss_smp2p_out 0>,
|
||||
+ <&wcss_smp2p_out 1>;
|
||||
+ qcom,smem-state-names = "shutdown",
|
||||
+ "stop";
|
||||
+
|
||||
+ memory-region = <&q6_region>;
|
||||
+
|
||||
+ glink-edge {
|
||||
+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
|
||||
+ qcom,remote-pid = <1>;
|
||||
+ mboxes = <&apcs_glb 8>;
|
||||
+
|
||||
+ rpm_requests {
|
||||
+ qcom,glink-channels = "IPCRTR";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
timer {
|
||||
@@ -0,0 +1,135 @@
|
||||
From a67d1901741c162645eda0dbdc3a2c0c2aff5cf4 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Tue, 21 Dec 2021 14:49:36 +0100
|
||||
Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node
|
||||
|
||||
IPQ8074 has a AHB based Q6v5 802.11ax radios that are supported
|
||||
by the ath11k.
|
||||
|
||||
Add the required DT node to enable the built-in radios.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++
|
||||
1 file changed, 111 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -994,6 +994,117 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ wifi: wifi@c0000000 {
|
||||
+ compatible = "qcom,ipq8074-wifi";
|
||||
+ reg = <0xc000000 0x2000000>;
|
||||
+
|
||||
+ interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
|
||||
+
|
||||
+ interrupt-names = "misc-pulse1",
|
||||
+ "misc-latch",
|
||||
+ "sw-exception",
|
||||
+ "ce0",
|
||||
+ "ce1",
|
||||
+ "ce2",
|
||||
+ "ce3",
|
||||
+ "ce4",
|
||||
+ "ce5",
|
||||
+ "ce6",
|
||||
+ "ce7",
|
||||
+ "ce8",
|
||||
+ "ce9",
|
||||
+ "ce10",
|
||||
+ "ce11",
|
||||
+ "host2wbm-desc-feed",
|
||||
+ "host2reo-re-injection",
|
||||
+ "host2reo-command",
|
||||
+ "host2rxdma-monitor-ring3",
|
||||
+ "host2rxdma-monitor-ring2",
|
||||
+ "host2rxdma-monitor-ring1",
|
||||
+ "reo2ost-exception",
|
||||
+ "wbm2host-rx-release",
|
||||
+ "reo2host-status",
|
||||
+ "reo2host-destination-ring4",
|
||||
+ "reo2host-destination-ring3",
|
||||
+ "reo2host-destination-ring2",
|
||||
+ "reo2host-destination-ring1",
|
||||
+ "rxdma2host-monitor-destination-mac3",
|
||||
+ "rxdma2host-monitor-destination-mac2",
|
||||
+ "rxdma2host-monitor-destination-mac1",
|
||||
+ "ppdu-end-interrupts-mac3",
|
||||
+ "ppdu-end-interrupts-mac2",
|
||||
+ "ppdu-end-interrupts-mac1",
|
||||
+ "rxdma2host-monitor-status-ring-mac3",
|
||||
+ "rxdma2host-monitor-status-ring-mac2",
|
||||
+ "rxdma2host-monitor-status-ring-mac1",
|
||||
+ "host2rxdma-host-buf-ring-mac3",
|
||||
+ "host2rxdma-host-buf-ring-mac2",
|
||||
+ "host2rxdma-host-buf-ring-mac1",
|
||||
+ "rxdma2host-destination-ring-mac3",
|
||||
+ "rxdma2host-destination-ring-mac2",
|
||||
+ "rxdma2host-destination-ring-mac1",
|
||||
+ "host2tcl-input-ring4",
|
||||
+ "host2tcl-input-ring3",
|
||||
+ "host2tcl-input-ring2",
|
||||
+ "host2tcl-input-ring1",
|
||||
+ "wbm2host-tx-completions-ring3",
|
||||
+ "wbm2host-tx-completions-ring2",
|
||||
+ "wbm2host-tx-completions-ring1",
|
||||
+ "tcl2host-status-ring";
|
||||
+ qcom,rproc = <&q6v5_wcss>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
};
|
||||
|
||||
timer {
|
||||
@@ -0,0 +1,59 @@
|
||||
From cb3ef99c1553565e1dc0301ccd5c1c0fa2d15c15 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 31 Dec 2021 17:56:14 +0100
|
||||
Subject: [PATCH] arm64: dts: ipq8074: add CPU clock
|
||||
|
||||
Now that CPU clock is exposed and can be controlled, add the necessary
|
||||
properties to the CPU nodes.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
|
||||
+#include <dt-bindings/clock/qcom,apss-ipq.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
@@ -38,6 +39,8 @@
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
+ clock-names = "cpu";
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
@@ -46,6 +49,8 @@
|
||||
enable-method = "psci";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
+ clock-names = "cpu";
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
@@ -54,6 +59,8 @@
|
||||
enable-method = "psci";
|
||||
reg = <0x2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
+ clock-names = "cpu";
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
@@ -62,6 +69,8 @@
|
||||
enable-method = "psci";
|
||||
reg = <0x3>;
|
||||
next-level-cache = <&L2_0>;
|
||||
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
+ clock-names = "cpu";
|
||||
};
|
||||
|
||||
L2_0: l2-cache {
|
||||
@@ -0,0 +1,48 @@
|
||||
From 347ca56e86c99021fad059b9a8ef101245b8507e Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 31 Dec 2021 20:38:06 +0100
|
||||
Subject: [PATCH] arm64: dts: ipq8074: add cooling cells to CPU nodes
|
||||
|
||||
Since there is CPU Freq support as well as thermal sensor support
|
||||
now for the IPQ8074, add cooling cells to CPU nodes so that they can
|
||||
be used as cooling devices using CPU Freq.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -41,6 +41,7 @@
|
||||
enable-method = "psci";
|
||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
clock-names = "cpu";
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
@@ -51,6 +52,7 @@
|
||||
next-level-cache = <&L2_0>;
|
||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
clock-names = "cpu";
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
@@ -61,6 +63,7 @@
|
||||
next-level-cache = <&L2_0>;
|
||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
clock-names = "cpu";
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
@@ -71,6 +74,7 @@
|
||||
next-level-cache = <&L2_0>;
|
||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
clock-names = "cpu";
|
||||
+ #cooling-cells = <2>;
|
||||
};
|
||||
|
||||
L2_0: l2-cache {
|
||||
@@ -0,0 +1,108 @@
|
||||
From 11592aa862e67f4477dee7e94d5c8244d893de1b Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Sat, 31 Dec 2022 13:03:41 +0100
|
||||
Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
|
||||
|
||||
IPQ8074 comes in 2 families:
|
||||
* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
|
||||
* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
|
||||
|
||||
So, in order to be able to share one OPP table lets add support for IPQ8074
|
||||
family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
|
||||
|
||||
IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
|
||||
will get created by NVMEM CPUFreq driver.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
Changes in v2:
|
||||
* Print an error if SMEM ID is not part of the IPQ8074 family
|
||||
and restrict the speed to Acorn variant (1.4GHz)
|
||||
---
|
||||
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
|
||||
drivers/cpufreq/qcom-cpufreq-nvmem.c | 43 ++++++++++++++++++++++++++++
|
||||
2 files changed, 44 insertions(+)
|
||||
|
||||
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
|
||||
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
|
||||
@@ -164,6 +164,7 @@ static const struct of_device_id blockli
|
||||
{ .compatible = "ti,omap3", },
|
||||
|
||||
{ .compatible = "qcom,ipq8064", },
|
||||
+ { .compatible = "qcom,ipq8074", },
|
||||
{ .compatible = "qcom,apq8064", },
|
||||
{ .compatible = "qcom,msm8974", },
|
||||
{ .compatible = "qcom,msm8960", },
|
||||
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
|
||||
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
|
||||
@@ -31,6 +31,9 @@
|
||||
|
||||
#include <dt-bindings/arm/qcom,ids.h>
|
||||
|
||||
+#define IPQ8074_HAWKEYE_VERSION BIT(0)
|
||||
+#define IPQ8074_ACORN_VERSION BIT(1)
|
||||
+
|
||||
struct qcom_cpufreq_drv;
|
||||
|
||||
struct qcom_cpufreq_match_data {
|
||||
@@ -204,6 +207,41 @@ len_error:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
|
||||
+ struct nvmem_cell *speedbin_nvmem,
|
||||
+ char **pvs_name,
|
||||
+ struct qcom_cpufreq_drv *drv)
|
||||
+{
|
||||
+ u32 msm_id;
|
||||
+ int ret;
|
||||
+ *pvs_name = NULL;
|
||||
+
|
||||
+ ret = qcom_smem_get_soc_id(&msm_id);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ switch (msm_id) {
|
||||
+ case QCOM_ID_IPQ8070A:
|
||||
+ case QCOM_ID_IPQ8071A:
|
||||
+ drv->versions = IPQ8074_ACORN_VERSION;
|
||||
+ break;
|
||||
+ case QCOM_ID_IPQ8072A:
|
||||
+ case QCOM_ID_IPQ8074A:
|
||||
+ case QCOM_ID_IPQ8076A:
|
||||
+ case QCOM_ID_IPQ8078A:
|
||||
+ drv->versions = IPQ8074_HAWKEYE_VERSION;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(cpu_dev,
|
||||
+ "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
|
||||
+ msm_id);
|
||||
+ drv->versions = IPQ8074_ACORN_VERSION;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static const struct qcom_cpufreq_match_data match_data_kryo = {
|
||||
.get_version = qcom_cpufreq_kryo_name_version,
|
||||
};
|
||||
@@ -218,6 +256,10 @@ static const struct qcom_cpufreq_match_d
|
||||
.genpd_names = qcs404_genpd_names,
|
||||
};
|
||||
|
||||
+static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
|
||||
+ .get_version = qcom_cpufreq_ipq8074_name_version,
|
||||
+};
|
||||
+
|
||||
static int qcom_cpufreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_cpufreq_drv *drv;
|
||||
@@ -363,6 +405,7 @@ static const struct of_device_id qcom_cp
|
||||
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
|
||||
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
|
||||
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
|
||||
+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
|
||||
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
|
||||
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
|
||||
{ .compatible = "qcom,msm8960", .data = &match_data_krait },
|
||||
@@ -0,0 +1,128 @@
|
||||
From 04d2fc6a551bbd972a6428059b45ce79cb9de9d7 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Fri, 6 May 2022 22:38:24 +0200
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: add QFPROM fuses
|
||||
|
||||
Add the QFPROM node and CPR fuses.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 107 ++++++++++++++++++++++++++
|
||||
1 file changed, 107 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -340,6 +340,113 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ qfprom: efuse@a4000 {
|
||||
+ compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
|
||||
+ reg = <0x000a4000 0x1000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ cpr_efuse_speedbin: speedbin@125 {
|
||||
+ reg = <0x125 0x1>;
|
||||
+ bits = <0 3>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_boost_cfg: boost_cfg@125 {
|
||||
+ reg = <0x125 0x1>;
|
||||
+ bits = <3 3>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_misc_volt_adj: misc_volt_adj@125 {
|
||||
+ reg = <0x125 0x1>;
|
||||
+ bits = <3 3>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_boost_volt: boost_volt@126 {
|
||||
+ reg = <0x126 0x1>;
|
||||
+ bits = <6 1>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_revision: revision@23e {
|
||||
+ reg = <0x23e 0x1>;
|
||||
+ bits = <5 3>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_ro_sel0: rosel0@249 {
|
||||
+ reg = <0x249 0x1>;
|
||||
+ bits = <0 4>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_ro_sel1: rosel1@248 {
|
||||
+ reg = <0x248 0x1>;
|
||||
+ bits = <4 4>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_ro_sel2: rosel2@248 {
|
||||
+ reg = <0x248 0x2>;
|
||||
+ bits = <0 4>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_ro_sel3: rosel3@249 {
|
||||
+ reg = <0x249 0x1>;
|
||||
+ bits = <4 4>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_init_voltage0: ivoltage0@23a {
|
||||
+ reg = <0x23a 0x1>;
|
||||
+ bits = <2 6>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_init_voltage1: ivoltage1@239 {
|
||||
+ reg = <0x239 0x2>;
|
||||
+ bits = <4 6>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_init_voltage2: ivoltage2@238 {
|
||||
+ reg = <0x238 0x2>;
|
||||
+ bits = <6 6>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_init_voltage3: ivoltage3@238 {
|
||||
+ reg = <0x238 0x1>;
|
||||
+ bits = <0 6>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_quot0: quot0@244 {
|
||||
+ reg = <0x244 0x2>;
|
||||
+ bits = <0 12>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_quot1: quot1@242 {
|
||||
+ reg = <0x242 0x2>;
|
||||
+ bits = <4 12>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_quot2: quot2@241 {
|
||||
+ reg = <0x241 0x2>;
|
||||
+ bits = <0 12>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_quot3: quot3@245 {
|
||||
+ reg = <0x245 0x2>;
|
||||
+ bits = <4 12>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_quot0_offset: quot0_offset@23d {
|
||||
+ reg = <0x23d 0x2>;
|
||||
+ bits = <6 7>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_quot1_offset: quot1_offset@23c {
|
||||
+ reg = <0x23c 0x2>;
|
||||
+ bits = <7 7>;
|
||||
+ };
|
||||
+
|
||||
+ cpr_efuse_quot2_offset: quot2_offset@23c {
|
||||
+ reg = <0x23c 0x1>;
|
||||
+ bits = <0 7>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
prng: rng@e3000 {
|
||||
compatible = "qcom,prng-ee";
|
||||
reg = <0x000e3000 0x1000>;
|
||||
@@ -0,0 +1,102 @@
|
||||
From a20c4e8738a00087aa5d53fe5148ed484e23d229 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Sat, 31 Dec 2022 13:56:26 +0100
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: add CPU OPP table
|
||||
|
||||
Now that there is NVMEM CPUFreq support for IPQ8074, we can add the OPP
|
||||
table for SoC.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 52 +++++++++++++++++++++++++++
|
||||
1 file changed, 52 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -42,6 +42,7 @@
|
||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
clock-names = "cpu";
|
||||
#cooling-cells = <2>;
|
||||
+ operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
@@ -53,6 +54,7 @@
|
||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
clock-names = "cpu";
|
||||
#cooling-cells = <2>;
|
||||
+ operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
@@ -64,6 +66,7 @@
|
||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
clock-names = "cpu";
|
||||
#cooling-cells = <2>;
|
||||
+ operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
@@ -75,6 +78,7 @@
|
||||
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
||||
clock-names = "cpu";
|
||||
#cooling-cells = <2>;
|
||||
+ operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
L2_0: l2-cache {
|
||||
@@ -83,6 +87,54 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ cpu_opp_table: opp-table {
|
||||
+ compatible = "operating-points-v2-kryo-cpu";
|
||||
+ nvmem-cells = <&cpr_efuse_speedbin>;
|
||||
+ opp-shared;
|
||||
+
|
||||
+ opp-1017600000 {
|
||||
+ opp-hz = /bits/ 64 <1017600000>;
|
||||
+ opp-microvolt = <1>;
|
||||
+ opp-supported-hw = <0xf>;
|
||||
+ clock-latency-ns = <200000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1382400000 {
|
||||
+ opp-hz = /bits/ 64 <1382400000>;
|
||||
+ opp-microvolt = <2>;
|
||||
+ opp-supported-hw = <0xf>;
|
||||
+ clock-latency-ns = <200000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1651200000 {
|
||||
+ opp-hz = /bits/ 64 <1651200000>;
|
||||
+ opp-microvolt = <3>;
|
||||
+ opp-supported-hw = <0x1>;
|
||||
+ clock-latency-ns = <200000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1843200000 {
|
||||
+ opp-hz = /bits/ 64 <1843200000>;
|
||||
+ opp-microvolt = <4>;
|
||||
+ opp-supported-hw = <0x1>;
|
||||
+ clock-latency-ns = <200000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1920000000 {
|
||||
+ opp-hz = /bits/ 64 <1920000000>;
|
||||
+ opp-microvolt = <5>;
|
||||
+ opp-supported-hw = <0x1>;
|
||||
+ clock-latency-ns = <200000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-2208000000 {
|
||||
+ opp-hz = /bits/ 64 <2208000000>;
|
||||
+ opp-microvolt = <6>;
|
||||
+ opp-supported-hw = <0x1>;
|
||||
+ clock-latency-ns = <200000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
@@ -0,0 +1,36 @@
|
||||
From f5aaf6669bd4f1f0218dd7fd5dc90941267ad860 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Tue, 30 May 2023 23:26:30 +0200
|
||||
Subject: [PATCH] mmc: core: disable TRIM on Micron MTFC4GACAJCN-1M
|
||||
|
||||
It seems that Micron MTFC4GACAJCN-1M despite advertising TRIM support does
|
||||
not work when the core is trying to use REQ_OP_WRITE_ZEROES.
|
||||
|
||||
We are seeing the following errors in OpenWrt under 6.1 on Qnap Qhora 301W
|
||||
that we did not previously have and tracked it down to REQ_OP_WRITE_ZEROES:
|
||||
[ 18.085950] I/O error, dev loop0, sector 596 op 0x9:(WRITE_ZEROES) flags 0x800 phys_seg 0 prio class 2
|
||||
|
||||
Disabling TRIM makes the error go away, so lets add a quirk for this eMMC
|
||||
to disable TRIM.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
drivers/mmc/core/quirks.h | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/drivers/mmc/core/quirks.h
|
||||
+++ b/drivers/mmc/core/quirks.h
|
||||
@@ -101,6 +101,13 @@ static const struct mmc_fixup __maybe_un
|
||||
MMC_QUIRK_TRIM_BROKEN),
|
||||
|
||||
/*
|
||||
+ * Micron MTFC4GACAJCN-1M advertises TRIM but it does not seems to
|
||||
+ * support being used to offload WRITE_ZEROES.
|
||||
+ */
|
||||
+ MMC_FIXUP("Q2J54A", CID_MANFID_MICRON, 0x014e, add_quirk_mmc,
|
||||
+ MMC_QUIRK_TRIM_BROKEN),
|
||||
+
|
||||
+ /*
|
||||
* Some SD cards reports discard support while they don't
|
||||
*/
|
||||
MMC_FIXUP(CID_NAME_ANY, CID_MANFID_SANDISK_SD, 0x5344, add_quirk_sd,
|
||||
@@ -0,0 +1,38 @@
|
||||
From 26c97b6fb7d291f55e0e4a410d266d1355118ed9 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Wed, 31 May 2023 20:21:26 +0200
|
||||
Subject: [PATCH] mmc: core: disable TRIM on Kingston EMMC04G-M627
|
||||
|
||||
It seems that Kingston EMMC04G-M627 despite advertising TRIM support does
|
||||
not work when the core is trying to use REQ_OP_WRITE_ZEROES.
|
||||
|
||||
We are seeing I/O errors in OpenWrt under 6.1 on Zyxel NBG7815 that we did
|
||||
not previously have and tracked it down to REQ_OP_WRITE_ZEROES.
|
||||
|
||||
Trying to use fstrim seems to also throw errors like:
|
||||
[93010.835112] I/O error, dev loop0, sector 16902 op 0x3:(DISCARD) flags 0x800 phys_seg 1 prio class 2
|
||||
|
||||
Disabling TRIM makes the error go away, so lets add a quirk for this eMMC
|
||||
to disable TRIM.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
drivers/mmc/core/quirks.h | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/drivers/mmc/core/quirks.h
|
||||
+++ b/drivers/mmc/core/quirks.h
|
||||
@@ -108,6 +108,13 @@ static const struct mmc_fixup __maybe_un
|
||||
MMC_QUIRK_TRIM_BROKEN),
|
||||
|
||||
/*
|
||||
+ * Kingston EMMC04G-M627 advertises TRIM but it does not seems to
|
||||
+ * support being used to offload WRITE_ZEROES.
|
||||
+ */
|
||||
+ MMC_FIXUP("M62704", CID_MANFID_KINGSTON, 0x0100, add_quirk_mmc,
|
||||
+ MMC_QUIRK_TRIM_BROKEN),
|
||||
+
|
||||
+ /*
|
||||
* Some SD cards reports discard support while they don't
|
||||
*/
|
||||
MMC_FIXUP(CID_NAME_ANY, CID_MANFID_SANDISK_SD, 0x5344, add_quirk_sd,
|
||||
@@ -0,0 +1,197 @@
|
||||
From 145bbf2b88990ef3ff00ee541bb7662008683c16 Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Wed, 7 Jun 2023 20:26:26 +0200
|
||||
Subject: [PATCH] arm64: dts: qcom: ipq8074: add critical thermal trips
|
||||
|
||||
According to bindings, thermal zones must have associated trips as well.
|
||||
Since we currently dont have CPUFreq support and thus no passive cooling
|
||||
lets start by defining critical trips to protect the devices against
|
||||
severe overheating.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
|
||||
1 file changed, 96 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -1293,6 +1293,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 4>;
|
||||
+
|
||||
+ trips {
|
||||
+ nss-top-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
nss0-thermal {
|
||||
@@ -1300,6 +1308,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 5>;
|
||||
+
|
||||
+ trips {
|
||||
+ nss-0-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
nss1-thermal {
|
||||
@@ -1307,6 +1323,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 6>;
|
||||
+
|
||||
+ trips {
|
||||
+ nss-1-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
wcss-phya0-thermal {
|
||||
@@ -1314,6 +1338,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 7>;
|
||||
+
|
||||
+ trips {
|
||||
+ wcss-phya0-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
wcss-phya1-thermal {
|
||||
@@ -1321,6 +1353,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 8>;
|
||||
+
|
||||
+ trips {
|
||||
+ wcss-phya1-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
cpu0_thermal: cpu0-thermal {
|
||||
@@ -1328,6 +1368,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 9>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu0-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
cpu1_thermal: cpu1-thermal {
|
||||
@@ -1335,6 +1383,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 10>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu1-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
cpu2_thermal: cpu2-thermal {
|
||||
@@ -1342,6 +1398,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 11>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu2-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
cpu3_thermal: cpu3-thermal {
|
||||
@@ -1349,6 +1413,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 12>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu3-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
cluster_thermal: cluster-thermal {
|
||||
@@ -1356,6 +1428,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 13>;
|
||||
+
|
||||
+ trips {
|
||||
+ cluster-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
wcss-phyb0-thermal {
|
||||
@@ -1363,6 +1443,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 14>;
|
||||
+
|
||||
+ trips {
|
||||
+ wcss-phyb0-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
wcss-phyb1-thermal {
|
||||
@@ -1370,6 +1458,14 @@
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 15>;
|
||||
+
|
||||
+ trips {
|
||||
+ wcss-phyb1-crit {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <1000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,24 @@
|
||||
From 6baf7e4abcea6f7ac21eccf072a20078b39d064c Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robimarko@gmail.com>
|
||||
Date: Wed, 9 Feb 2022 23:13:26 +0100
|
||||
Subject: [PATCH] arm64: dts: ipq8074: add label to clocks
|
||||
|
||||
Add label to clocks node as that makes it easy to add the NSS fixed
|
||||
clocks that are required in their DTSI.
|
||||
|
||||
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||||
@@ -15,7 +15,7 @@
|
||||
compatible = "qcom,ipq8074";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
- clocks {
|
||||
+ clocks: clocks {
|
||||
sleep_clk: sleep_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
Reference in New Issue
Block a user