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forked from Ivasoft/openwrt

lantiq: copy target to kernel 4.19

This just copies the files from the kernel 4.14 specific folders into
the kernel 4.19 specific folder, no changes are done to the files in
this commit.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Hauke Mehrtens
2018-11-25 19:35:16 +01:00
committed by Mathias Kresin
parent bf21b6e44d
commit eee1b34ce6
116 changed files with 14836 additions and 0 deletions

View File

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#include "vr9.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/mips/lantiq_rcu_gphy.h>
/ {
compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9";
chosen {
bootargs = "console=ttyLTQ0,115200";
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
led-usb = &led_usb1;
led-usb2 = &led_usb2;
};
memory@0 {
reg = <0x0 0x4000000>;
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
/* reset {
label = "reset";
gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};*/
paging {
label = "paging";
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PHONE>;
};
};
gpio-leds {
compatible = "gpio-leds";
power: power {
label = "easy80920:green:power";
gpios = <&stp 9 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
warning {
label = "easy80920:green:warning";
gpios = <&stp 22 GPIO_ACTIVE_HIGH>;
};
fxs1 {
label = "easy80920:green:fxs1";
gpios = <&stp 21 GPIO_ACTIVE_HIGH>;
};
fxs2 {
label = "easy80920:green:fxs2";
gpios = <&stp 20 GPIO_ACTIVE_HIGH>;
};
fxo {
label = "easy80920:green:fxo";
gpios = <&stp 19 GPIO_ACTIVE_HIGH>;
};
led_usb1: usb1 {
label = "easy80920:green:usb1";
gpios = <&stp 18 GPIO_ACTIVE_HIGH>;
};
led_usb2: usb2 {
label = "easy80920:green:usb2";
gpios = <&stp 15 GPIO_ACTIVE_HIGH>;
};
sd {
label = "easy80920:green:sd";
gpios = <&stp 14 GPIO_ACTIVE_HIGH>;
};
wps {
label = "easy80920:green:wps";
gpios = <&stp 12 GPIO_ACTIVE_HIGH>;
};
};
usb_vbus: regulator-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&eth0 {
lan: interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
lantiq,switch;
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
};
wan: interface@1 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
lantiq,wan;
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
reg = <0>;
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <0x5>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
&gphy1 {
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
exin3 {
lantiq,groups = "exin3";
lantiq,function = "exin";
};
stp {
lantiq,groups = "stp";
lantiq,function = "stp";
};
nand {
lantiq,groups = "nand cle", "nand ale",
"nand rd", "nand rdy";
lantiq,function = "ebu";
};
mdio {
lantiq,groups = "mdio";
lantiq,function = "mdio";
};
pci {
lantiq,groups = "gnt1", "req1";
lantiq,function = "pci";
};
conf_out {
lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
"io4", "io5", "io6", /* stp */
"io21",
"io33";
lantiq,open-drain;
lantiq,pull = <0>;
lantiq,output = <1>;
};
pcie-rst {
lantiq,pins = "io38";
lantiq,pull = <0>;
lantiq,output = <1>;
};
conf_in {
lantiq,pins = "io39", /* exin3 */
"io48"; /* nand rdy */
lantiq,pull = <2>;
};
};
pins_spi_default: pins_spi_default {
spi_in {
lantiq,groups = "spi_di";
lantiq,function = "spi";
};
spi_out {
lantiq,groups = "spi_do", "spi_clk",
"spi_cs4";
lantiq,function = "spi";
lantiq,output = <1>;
};
};
};
&spi {
pinctrl-names = "default";
pinctrl-0 = <&pins_spi_default>;
status = "okay";
m25p80@4 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <4 0>;
spi-max-frequency = <1000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x20000>;
label = "SPI (RO) U-Boot Image";
read-only;
};
partition@20000 {
reg = <0x20000 0x10000>;
label = "ENV_MAC";
read-only;
};
partition@30000 {
reg = <0x30000 0x10000>;
label = "DPF";
read-only;
};
partition@40000 {
reg = <0x40000 0x10000>;
label = "NVRAM";
read-only;
};
partition@500000 {
reg = <0x50000 0x003a0000>;
label = "kernel";
};
};
};
};
&stp {
status = "okay";
lantiq,shadow = <0xffff>;
lantiq,groups = <0x7>;
lantiq,dsl = <0x3>;
lantiq,phy1 = <0x7>;
lantiq,phy2 = <0x7>;
/* lantiq,rising; */
};
&usb_phy0 {
status = "okay";
};
&usb0 {
status = "okay";
vbus-supply = <&usb_vbus>;
};