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ar71xx: add AR933x specific frequency initialization code

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SVN-Revision: 27056
This commit is contained in:
Gabor Juhos
2011-05-31 22:53:29 +00:00
parent 0bf4478d37
commit e11b9c8371
2 changed files with 76 additions and 0 deletions
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21
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
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@@ -188,6 +188,24 @@ extern enum ar71xx_soc_type ar71xx_soc;
#define AR91XX_ETH0_PLL_SHIFT 20
#define AR91XX_ETH1_PLL_SHIFT 22
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
#define AR934X_PLL_REG_CPU_CONFIG 0x00
#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
@@ -579,6 +597,9 @@ void ar71xx_ddr_flush(u32 reg);
#define AR724X_RESET_REG_RESET_MODULE 0x1c
#define AR933X_RESET_REG_BOOTSTRAP 0xac
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_RESET_REG_RESET_MODULE 0x1c
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
/* 0 - 25MHz 1 - 40 MHz */