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move files to files-3.7

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Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 36161
This commit is contained in:
John Crispin
2013-04-03 09:58:44 +00:00
parent 86a691144b
commit d4db00205d
144 changed files with 0 additions and 0 deletions
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27
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/common.h
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@@ -1,27 +0,0 @@
/*
* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_RALINK_COMMON_H
#define __ASM_MACH_RALINK_COMMON_H
#define RAMIPS_SYS_TYPE_LEN 64
extern unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN];
extern unsigned long ramips_mem_base;
extern unsigned long ramips_mem_size_min;
extern unsigned long ramips_mem_size_max;
extern unsigned long (*ramips_get_mem_size)(void);
void ramips_intc_irq_init(unsigned intc_base, unsigned irq, unsigned irq_base);
u32 ramips_intc_get_status(void);
void ramips_soc_prom_init(void);
void ramips_soc_setup(void);
void ramips_early_serial_setup(int line, unsigned base, unsigned freq,
unsigned irq);
#endif /* __ASM_MACH_RALINK_COMMON_H */

29
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/dev-gpio-buttons.h
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@@ -1,29 +0,0 @@
/*
* Ralink SoC GPIO button support
*
* Copyright (C) 2010-2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H
#define __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H
#include <linux/input.h>
#include <linux/gpio_keys.h>
#ifdef CONFIG_RALINK_DEV_GPIO_BUTTONS
void
ramips_register_gpio_buttons(int id, unsigned poll_interval, unsigned nbuttons,
struct gpio_keys_button *buttons);
#else
static inline void
ramips_register_gpio_buttons(int id, unsigned poll_interval, unsigned nbuttons,
struct gpio_keys_button *buttons)
{
}
#endif
#endif /* __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H */

26
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/dev-gpio-leds.h
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@@ -1,26 +0,0 @@
/*
* Ralink SoC GPIO LED device support
*
* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_RALINK_DEV_GPIO_LEDS_H
#define __ASM_MACH_RALINK_DEV_GPIO_LEDS_H
#include <linux/leds.h>
#ifdef CONFIG_RALINK_DEV_GPIO_LEDS
void ramips_register_gpio_leds(int id, unsigned num_leds,
struct gpio_led *leds);
#else
static inline void ramips_register_gpio_leds(int id, unsigned num_leds,
struct gpio_led *leds)
{
}
#endif
#endif /* __ASM_MACH_RALINK_DEV_GPIO_LEDS_H */

24
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/gpio.h
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@@ -1,24 +0,0 @@
/*
* Ralink SoC GPIO API support
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef __ASM_MACH_RALINK_GPIO_H
#define __ASM_MACH_RALINK_GPIO_H
#define ARCH_NR_GPIOS 128
#include <asm-generic/gpio.h>
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
#endif /* __ASM_MACH_RALINK_GPIO_H */

88
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/machine.h
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@@ -1,88 +0,0 @@
/*
* Ralink machine types
*
* Copyright (C) 2010 Joonas Lahtinen <joonas.lahtinen@gmail.com>
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <asm/mips_machine.h>
enum ramips_mach_type {
RAMIPS_MACH_GENERIC,
/* RT2880 based machines */
RAMIPS_MACH_F5D8235_V1, /* Belkin F5D8235 v1 */
RAMIPS_MACH_BR6524N, /* Edimax BR6524N */
RAMIPS_MACH_RT_N15, /* Asus RT-N15 */
RAMIPS_MACH_V11ST_FE, /* Ralink V11ST-FE */
RAMIPS_MACH_WLI_TX4_AG300N, /* Buffalo WLI-TX4-AG300N */
RAMIPS_MACH_WZR_AGL300NH, /* Buffalo WZR-AGL300NH */
/* RT3050 based machines */
RAMIPS_MACH_3G_6200N, /* Edimax 3G-6200N */
RAMIPS_MACH_ALL0256N, /* Allnet ALL0256N */
RAMIPS_MACH_CARAMBOLA, /* 8devices Carambola */
RAMIPS_MACH_DIR_300_B1, /* D-Link DIR-300 B1 */
RAMIPS_MACH_DIR_600_B1, /* D-Link DIR-600 B1 */
RAMIPS_MACH_DIR_600_B2, /* D-Link DIR-600 B2 */
RAMIPS_MACH_DIR_615_D, /* D-Link DIR-615 D */
RAMIPS_MACH_DIR_620_A1, /* D-Link DIR-620 A1 */
RAMIPS_MACH_RT_G32_B1, /* Asus RT-G32 B1 */
RAMIPS_MACH_RT_N10_PLUS, /* Asus RT-N10+ */
RAMIPS_MACH_NW718, /* Netcore NW718 */
RAMIPS_MACH_WL_330N, /* Asus WL-330N */
RAMIPS_MACH_WL_330N3G, /* Asus WL-330N3G */
/* RT3052 based machines */
RAMIPS_MACH_3G300M, /* Tenda 3G300M */
RAMIPS_MACH_ALL0239_3G, /* ALL0239-3G */
RAMIPS_MACH_ARGUS_ATP52B, /* Argus ATP-52B */
RAMIPS_MACH_BC2, /* NexAira BC2 */
RAMIPS_MACH_BR6425, /* Edimax BR-6425 */
RAMIPS_MACH_BROADWAY, /* Hauppauge Broadway */
RAMIPS_MACH_DAP_1350, /* D-Link DAP-1350 */
RAMIPS_MACH_ESR_9753, /* Senao / EnGenius ESR-9753*/
RAMIPS_MACH_F5D8235_V2, /* Belkin F5D8235 v2 */
RAMIPS_MACH_FONERA20N, /* La Fonera 2.0N */
RAMIPS_MACH_RT_N13U, /* ASUS RT-N13U */
RAMIPS_MACH_FREESTATION5, /* ARC Freestation5 */
RAMIPS_MACH_HW550_3G, /* Aztech HW550-3G */
RAMIPS_MACH_MOFI3500_3GN, /* MoFi Network MOFI3500-3GN */
RAMIPS_MACH_NBG_419N, /* ZyXEL NBG-419N */
RAMIPS_MACH_OMNI_EMB, /* Omnima MiniEMBWiFi */
RAMIPS_MACH_PSR_680W, /* Petatel PSR-680W Wireless 3G Router*/
RAMIPS_MACH_PWH2004, /* Prolink 2004H / Abocom 5205 */
RAMIPS_MACH_SL_R7205, /* Skylink SL-R7205 Wireless 3G Router*/
RAMIPS_MACH_V22RW_2X2, /* Ralink AP-RT3052-V22RW-2X2 */
RAMIPS_MACH_W306R_V20, /* Tenda W306R_V20 */
RAMIPS_MACH_W502U, /* ALFA Networks W502U */
RAMIPS_MACH_WCR150GN, /* Sparklan WCR-150GN */
RAMIPS_MACH_WHR_G300N, /* Buffalo WHR-G300N */
RAMIPS_MACH_WL341V3, /* Sitecom WL-341 v3 */
RAMIPS_MACH_WL351, /* Sitecom WL-351 v1 002 */
RAMIPS_MACH_WR512_3GN, /* SH-WR512NU/WS-WR512N1-like 3GN*/
RAMIPS_MACH_WR6202, /* Accton WR6202 */
RAMIPS_MACH_MZKW300NH2, /* Planex MZK-W300NH2 Router */
RAMIPS_MACH_XDXRN502J, /* unknown XDX-RN502J */
RAMIPS_MACH_UR_326N4G, /* UPVEL ROUTER */
RAMIPS_MACH_UR_336UN, /* UPVEL ROUTER */
/* RT3352 based machines */
RAMIPS_MACH_ALL5002, /* Allnet ALL5002 */
RAMIPS_MACH_DIR_615_H1,
/* RT3662 based machines */
RAMIPS_MACH_DIR_645, /* D-Link DIR-645 */
RAMIPS_MACH_OMNI_EMB_HPM, /* Omnima EMB HPM */
RAMIPS_MACH_RT_N56U, /* Asus RT-N56U */
/* RT3883 based machines */
RAMIPS_MACH_TEW_691GR, /* TRENDnet TEW-691GR */
RAMIPS_MACH_TEW_692GR, /* TRENDnet TEW-692GR */
/* RT5350 based machines */
RAMIPS_MACH_AIR3GII, /* AirLive Air3GII */
};

41
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h
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@@ -1,41 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* based on Ralink SDK3.3
* Copyright (C) 2009 John Crispin <blogic@openwrt.org>
*/
#ifndef _RAMIPS_ETH_PLATFORM_H
#define _RAMIPS_ETH_PLATFORM_H
#include <linux/phy.h>
struct ramips_eth_platform_data
{
unsigned char mac[6];
void (*reset_fe)(void);
int min_pkt_len;
unsigned long sys_freq;
int speed;
int duplex;
int tx_fc;
int rx_fc;
u32 phy_mask;
phy_interface_t phy_if_mode;
};
#endif /* _RAMIPS_ETH_PLATFORM_H */

48
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_gpio.h
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@@ -1,48 +0,0 @@
/*
* Ralink SoC specific GPIO support
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RAMIPS_GPIO_H
#define _RAMIPS_GPIO_H
#include <linux/gpio.h>
#include <linux/spinlock.h>
enum ramips_gpio_reg {
RAMIPS_GPIO_REG_INT = 0, /* Interrupt status */
RAMIPS_GPIO_REG_EDGE,
RAMIPS_GPIO_REG_RENA,
RAMIPS_GPIO_REG_FENA,
RAMIPS_GPIO_REG_DATA,
RAMIPS_GPIO_REG_DIR, /* Direction, 0:in, 1: out */
RAMIPS_GPIO_REG_POL, /* Polarity, 0: normal, 1: invert */
RAMIPS_GPIO_REG_SET,
RAMIPS_GPIO_REG_RESET,
RAMIPS_GPIO_REG_TOGGLE,
RAMIPS_GPIO_REG_MAX
};
struct ramips_gpio_chip {
struct gpio_chip chip;
unsigned long map_base;
unsigned long map_size;
u8 regs[RAMIPS_GPIO_REG_MAX];
spinlock_t lock;
void __iomem *regs_base;
};
struct ramips_gpio_data {
unsigned int num_chips;
struct ramips_gpio_chip *chips;
};
int ramips_gpio_init(struct ramips_gpio_data *data);
#endif /* _RAMIPS_GPIO_H */

23
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h
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@@ -1,23 +0,0 @@
/*
* Platform data definition for the built-in NAND controller of the
* Ralink RT305X/RT3662/RT3883 SoCs
*
* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RAMIPS_NAND_PLATFORM_H
#define _RAMIPS_NAND_PLATFORM_H
#define RAMIPS_NAND_DRIVER_NAME "ramips-nand"
struct ramips_nand_platform_data {
const char *name;
struct mtd_partition *parts;
int nr_parts;
};
#endif /* _RAMIPS_NAND_PLATFORM_H */

76
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h
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@@ -1,76 +0,0 @@
/*
* Ralink RT288x SoC specific definitions
*
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Ralink's 2.6.21 BSP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RT288X_H_
#define _RT288X_H_
#include <linux/init.h>
#include <linux/io.h>
#define RT288X_MEM_SIZE_MIN (2 * 1024 * 1024)
#define RT288X_MEM_SIZE_MAX (128 * 1024 * 1024)
#define RT288X_CPU_IRQ_BASE 0
#define RT288X_INTC_IRQ_BASE 8
#define RT288X_INTC_IRQ_COUNT 32
#define RT288X_GPIO_IRQ_BASE 40
#define RT288X_CPU_IRQ_INTC (RT288X_CPU_IRQ_BASE + 2)
#define RT288X_CPU_IRQ_PCI (RT288X_CPU_IRQ_BASE + 4)
#define RT288X_CPU_IRQ_FE (RT288X_CPU_IRQ_BASE + 5)
#define RT288X_CPU_IRQ_WNIC (RT288X_CPU_IRQ_BASE + 6)
#define RT288X_CPU_IRQ_COUNTER (RT288X_CPU_IRQ_BASE + 7)
#define RT2880_INTC_IRQ_TIMER0 (RT288X_INTC_IRQ_BASE + 0)
#define RT2880_INTC_IRQ_TIMER1 (RT288X_INTC_IRQ_BASE + 1)
#define RT2880_INTC_IRQ_UART0 (RT288X_INTC_IRQ_BASE + 2)
#define RT2880_INTC_IRQ_PIO (RT288X_INTC_IRQ_BASE + 3)
#define RT2880_INTC_IRQ_PCM (RT288X_INTC_IRQ_BASE + 4)
#define RT2880_INTC_IRQ_UART1 (RT288X_INTC_IRQ_BASE + 8)
#define RT2880_INTC_IRQ_IA (RT288X_INTC_IRQ_BASE + 23)
#define RT288X_GPIO_IRQ(x) (RT288X_GPIO_IRQ_BASE + (x))
#define RT288X_GPIO_COUNT 32
extern void __iomem *rt288x_sysc_base;
extern void __iomem *rt288x_memc_base;
static inline void rt288x_sysc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt288x_sysc_base + reg);
}
static inline u32 rt288x_sysc_rr(unsigned reg)
{
return __raw_readl(rt288x_sysc_base + reg);
}
static inline void rt288x_memc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt288x_memc_base + reg);
}
static inline u32 rt288x_memc_rr(unsigned reg)
{
return __raw_readl(rt288x_memc_base + reg);
}
void rt288x_gpio_init(u32 mode);
#ifdef CONFIG_PCI
int rt288x_register_pci(void);
#else
static inline int rt288x_register_pci(void) { return 0; }
#endif /* CONFIG_PCI */
#endif /* _RT228X_H_ */

56
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
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@@ -1,56 +0,0 @@
/*
* Ralink RT288x specific CPU feature overrides
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_sb1_cache 0
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_prefetch 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 1
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 16
#define cpu_icache_line_size() 16
#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */

17
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/irq.h
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@@ -1,17 +0,0 @@
/*
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_RALINK_RT288X_IRQ_H
#define __ASM_MACH_RALINK_RT288X_IRQ_H
#define MIPS_CPU_IRQ_BASE 0
#define NR_IRQS 48
#include_next <irq.h>
#endif /* __ASM_MACH_RALINK_RT288X_IRQ_H */

127
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
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@@ -1,127 +0,0 @@
/*
* Ralink RT288x SoC register definitions
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RT288X_REGS_H_
#define _RT288X_REGS_H_
#include <linux/bitops.h>
#define RT2880_SYSC_BASE 0x00300000
#define RT2880_TIMER_BASE 0x00300100
#define RT2880_INTC_BASE 0x00300200
#define RT2880_MEMC_BASE 0x00300300
#define RT2880_UART0_BASE 0x00300500
#define RT2880_PIO_BASE 0x00300600
#define RT2880_I2C_BASE 0x00300900
#define RT2880_SPI_BASE 0x00300b00
#define RT2880_UART1_BASE 0x00300c00
#define RT2880_FE_BASE 0x00400000
#define RT2880_ROM_BASE 0x00410000
#define RT2880_PCM_BASE 0x00420000
#define RT2880_PCI_BASE 0x00440000
#define RT2880_WMAC_BASE 0x00480000
#define RT2880_FLASH1_BASE 0x01000000
#define RT2880_FLASH0_BASE 0x1dc00000
#define RT2880_SDRAM_BASE 0x08000000
#define RT2880_SYSC_SIZE 0x100
#define RT2880_TIMER_SIZE 0x100
#define RT2880_INTC_SIZE 0x100
#define RT2880_MEMC_SIZE 0x100
#define RT2880_UART0_SIZE 0x100
#define RT2880_PIO_SIZE 0x100
#define RT2880_UART1_SIZE 0x100
#define RT2880_FLASH1_SIZE (16 * 1024 * 1024)
#define RT2880_FLASH0_SIZE (32 * 1024 * 1024)
/* SYSC registers */
#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */
#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
#define SYSC_REG_CLKCFG 0x030
#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
#define CHIP_ID_ID_MASK 0xff
#define CHIP_ID_ID_SHIFT 8
#define CHIP_ID_REV_MASK 0xff
#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
#define SYSTEM_CONFIG_CPUCLK_250 0x0
#define SYSTEM_CONFIG_CPUCLK_266 0x1
#define SYSTEM_CONFIG_CPUCLK_280 0x2
#define SYSTEM_CONFIG_CPUCLK_300 0x3
#define CLKCFG_SRAM_CS_N_WDT BIT(9)
#define RT2880_RESET_SYSTEM BIT(0)
#define RT2880_RESET_TIMER BIT(1)
#define RT2880_RESET_INTC BIT(2)
#define RT2880_RESET_MEMC BIT(3)
#define RT2880_RESET_CPU BIT(4)
#define RT2880_RESET_UART0 BIT(5)
#define RT2880_RESET_PIO BIT(6)
#define RT2880_RESET_I2C BIT(9)
#define RT2880_RESET_SPI BIT(11)
#define RT2880_RESET_UART1 BIT(12)
#define RT2880_RESET_PCI BIT(16)
#define RT2880_RESET_WMAC BIT(17)
#define RT2880_RESET_FE BIT(18)
#define RT2880_RESET_PCM BIT(19)
#define RT2880_GPIO_MODE_I2C BIT(0)
#define RT2880_GPIO_MODE_UART0 BIT(1)
#define RT2880_GPIO_MODE_SPI BIT(2)
#define RT2880_GPIO_MODE_UART1 BIT(3)
#define RT2880_GPIO_MODE_JTAG BIT(4)
#define RT2880_GPIO_MODE_MDIO BIT(5)
#define RT2880_GPIO_MODE_SDRAM BIT(6)
#define RT2880_GPIO_MODE_PCI BIT(7)
#define RT2880_INTC_INT_TIMER0 BIT(0)
#define RT2880_INTC_INT_TIMER1 BIT(1)
#define RT2880_INTC_INT_UART0 BIT(2)
#define RT2880_INTC_INT_PIO BIT(3)
#define RT2880_INTC_INT_PCM BIT(4)
#define RT2880_INTC_INT_UART1 BIT(8)
#define RT2880_INTC_INT_IA BIT(23)
#define RT2880_INTC_INT_GLOBAL BIT(31)
/* MEMC registers */
#define MEMC_REG_SDRAM_CFG0 0x00
#define MEMC_REG_SDRAM_CFG1 0x04
#define MEMC_REG_FLASH_CFG0 0x08
#define MEMC_REG_FLASH_CFG1 0x0c
#define MEMC_REG_IA_ADDR 0x10
#define MEMC_REG_IA_TYPE 0x14
#define FLASH_CFG_WIDTH_SHIFT 26
#define FLASH_CFG_WIDTH_MASK 0x3
#define FLASH_CFG_WIDTH_8BIT 0x0
#define FLASH_CFG_WIDTH_16BIT 0x1
#define FLASH_CFG_WIDTH_32BIT 0x2
/* UART registers */
#define UART_REG_RX 0
#define UART_REG_TX 1
#define UART_REG_IER 2
#define UART_REG_IIR 3
#define UART_REG_FCR 4
#define UART_REG_LCR 5
#define UART_REG_MCR 6
#define UART_REG_LSR 7
#endif /* _RT288X_REGS_H_ */

169
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
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@@ -1,169 +0,0 @@
/*
* Ralink RT305x SoC specific definitions
*
* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
*
* Parts of this file are based on Ralink's 2.6.21 BSP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RT305X_H_
#define _RT305X_H_
#include <linux/init.h>
#include <linux/io.h>
enum rt305x_soc_type {
RT305X_SOC_UNKNOWN = 0,
RT305X_SOC_RT3050,
RT305X_SOC_RT3052,
RT305X_SOC_RT3350,
RT305X_SOC_RT3352,
RT305X_SOC_RT5350,
};
extern enum rt305x_soc_type rt305x_soc;
static inline int soc_is_rt3050(void)
{
return rt305x_soc == RT305X_SOC_RT3050;
}
static inline int soc_is_rt3052(void)
{
return rt305x_soc == RT305X_SOC_RT3052;
}
static inline int soc_is_rt305x(void)
{
return soc_is_rt3050() || soc_is_rt3052();
}
static inline int soc_is_rt3350(void)
{
return rt305x_soc == RT305X_SOC_RT3350;
}
static inline int soc_is_rt3352(void)
{
return rt305x_soc == RT305X_SOC_RT3352;
}
static inline int soc_is_rt5350(void)
{
return rt305x_soc == RT305X_SOC_RT5350;
}
#define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024)
#define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024)
#define RT3352_MEM_SIZE_MIN (2 * 1024 * 1024)
#define RT3352_MEM_SIZE_MAX (256 * 1024 * 1024)
#define RT305X_CPU_IRQ_BASE 0
#define RT305X_INTC_IRQ_BASE 8
#define RT305X_INTC_IRQ_COUNT 32
#define RT305X_GPIO_IRQ_BASE 40
#define RT305X_CPU_IRQ_INTC (RT305X_CPU_IRQ_BASE + 2)
#define RT305X_CPU_IRQ_FE (RT305X_CPU_IRQ_BASE + 5)
#define RT305X_CPU_IRQ_WNIC (RT305X_CPU_IRQ_BASE + 6)
#define RT305X_CPU_IRQ_COUNTER (RT305X_CPU_IRQ_BASE + 7)
#define RT305X_INTC_IRQ_SYSCTL (RT305X_INTC_IRQ_BASE + 0)
#define RT305X_INTC_IRQ_TIMER0 (RT305X_INTC_IRQ_BASE + 1)
#define RT305X_INTC_IRQ_TIMER1 (RT305X_INTC_IRQ_BASE + 2)
#define RT305X_INTC_IRQ_IA (RT305X_INTC_IRQ_BASE + 3)
#define RT305X_INTC_IRQ_PCM (RT305X_INTC_IRQ_BASE + 4)
#define RT305X_INTC_IRQ_UART0 (RT305X_INTC_IRQ_BASE + 5)
#define RT305X_INTC_IRQ_PIO (RT305X_INTC_IRQ_BASE + 6)
#define RT305X_INTC_IRQ_DMA (RT305X_INTC_IRQ_BASE + 7)
#define RT305X_INTC_IRQ_NAND (RT305X_INTC_IRQ_BASE + 8)
#define RT305X_INTC_IRQ_PERFC (RT305X_INTC_IRQ_BASE + 9)
#define RT305X_INTC_IRQ_I2S (RT305X_INTC_IRQ_BASE + 10)
#define RT305X_INTC_IRQ_UART1 (RT305X_INTC_IRQ_BASE + 12)
#define RT305X_INTC_IRQ_ESW (RT305X_INTC_IRQ_BASE + 17)
#define RT305X_INTC_IRQ_OTG (RT305X_INTC_IRQ_BASE + 18)
extern void __iomem *rt305x_sysc_base;
extern void __iomem *rt305x_memc_base;
static inline void rt305x_sysc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt305x_sysc_base + reg);
}
static inline u32 rt305x_sysc_rr(unsigned reg)
{
return __raw_readl(rt305x_sysc_base + reg);
}
static inline void rt305x_memc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt305x_memc_base + reg);
}
static inline u32 rt305x_memc_rr(unsigned reg)
{
return __raw_readl(rt305x_memc_base + reg);
}
#define RT305X_GPIO_I2C_SD 1
#define RT305X_GPIO_I2C_SCLK 2
#define RT305X_GPIO_SPI_EN 3
#define RT305X_GPIO_SPI_CLK 4
#define RT305X_GPIO_SPI_DOUT 5
#define RT305X_GPIO_SPI_DIN 6
/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
#define RT305X_GPIO_7 7
#define RT305X_GPIO_8 8
#define RT305X_GPIO_9 9
#define RT305X_GPIO_10 10
#define RT305X_GPIO_11 11
#define RT305X_GPIO_12 12
#define RT305X_GPIO_13 13
#define RT305X_GPIO_14 14
#define RT305X_GPIO_UART1_TXD 15
#define RT305X_GPIO_UART1_RXD 16
#define RT305X_GPIO_JTAG_TDO 17
#define RT305X_GPIO_JTAG_TDI 18
#define RT305X_GPIO_JTAG_TMS 19
#define RT305X_GPIO_JTAG_TCLK 20
#define RT305X_GPIO_JTAG_TRST_N 21
#define RT305X_GPIO_MDIO_MDC 22
#define RT305X_GPIO_MDIO_MDIO 23
#define RT305X_GPIO_SDRAM_MD16 24
#define RT305X_GPIO_SDRAM_MD17 25
#define RT305X_GPIO_SDRAM_MD18 26
#define RT305X_GPIO_SDRAM_MD19 27
#define RT305X_GPIO_SDRAM_MD20 28
#define RT305X_GPIO_SDRAM_MD21 29
#define RT305X_GPIO_SDRAM_MD22 30
#define RT305X_GPIO_SDRAM_MD23 31
#define RT305X_GPIO_SDRAM_MD24 32
#define RT305X_GPIO_SDRAM_MD25 33
#define RT305X_GPIO_SDRAM_MD26 34
#define RT305X_GPIO_SDRAM_MD27 35
#define RT305X_GPIO_SDRAM_MD28 36
#define RT305X_GPIO_SDRAM_MD29 37
#define RT305X_GPIO_SDRAM_MD30 38
#define RT305X_GPIO_SDRAM_MD31 39
#define RT305X_GPIO_GE0_TXD0 40
#define RT305X_GPIO_GE0_TXD1 41
#define RT305X_GPIO_GE0_TXD2 42
#define RT305X_GPIO_GE0_TXD3 43
#define RT305X_GPIO_GE0_TXEN 44
#define RT305X_GPIO_GE0_TXCLK 45
#define RT305X_GPIO_GE0_RXD0 46
#define RT305X_GPIO_GE0_RXD1 47
#define RT305X_GPIO_GE0_RXD2 48
#define RT305X_GPIO_GE0_RXD3 49
#define RT305X_GPIO_GE0_RXDV 50
#define RT305X_GPIO_GE0_RXCLK 51
void rt305x_gpio_init(u32 mode);
#endif /* _RT305X_H_ */

56
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
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@@ -1,56 +0,0 @@
/*
* Ralink RT305x specific CPU feature overrides
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_sb1_cache 0
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_prefetch 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 1
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 1
#define cpu_has_mipsmt 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */

17
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/irq.h
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@@ -1,17 +0,0 @@
/*
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_RALINK_RT305X_IRQ_H
#define __ASM_MACH_RALINK_RT305X_IRQ_H
#define MIPS_CPU_IRQ_BASE 0
#define NR_IRQS 48
#include_next <irq.h>
#endif /* __ASM_MACH_RALINK_RT305X_IRQ_H */

27
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
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@@ -1,27 +0,0 @@
/*
* Ralink RT305x SoC platform device registration
*
* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RT305X_ESW_PLATFORM_H
#define _RT305X_ESW_PLATFORM_H
enum {
RT305X_ESW_VLAN_CONFIG_NONE = 0,
RT305X_ESW_VLAN_CONFIG_LLLLW,
RT305X_ESW_VLAN_CONFIG_WLLLL,
};
struct rt305x_esw_platform_data
{
u8 vlan_config;
u32 reg_initval_fct2;
u32 reg_initval_fpa2;
};
#endif /* _RT305X_ESW_PLATFORM_H */

216
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
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@@ -1,216 +0,0 @@
/*
* Ralink RT305 SoC register definitions
*
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RT305X_REGS_H_
#define _RT305X_REGS_H_
#include <linux/bitops.h>
#define RT305X_SDRAM_BASE 0x00000000
#define RT305X_SYSC_BASE 0x10000000
#define RT305X_TIMER_BASE 0x10000100
#define RT305X_INTC_BASE 0x10000200
#define RT305X_MEMC_BASE 0x10000300
#define RT305X_PCM_BASE 0x10000400
#define RT305X_UART0_BASE 0x10000500
#define RT305X_PIO_BASE 0x10000600
#define RT305X_GDMA_BASE 0x10000700
#define RT305X_NANDC_BASE 0x10000800
#define RT305X_I2C_BASE 0x10000900
#define RT305X_I2S_BASE 0x10000a00
#define RT305X_SPI_BASE 0x10000b00
#define RT305X_UART1_BASE 0x10000c00
#define RT305X_FE_BASE 0x10100000
#define RT305X_SWITCH_BASE 0x10110000
#define RT305X_WMAC_BASE 0x10180000
#define RT305X_OTG_BASE 0x101c0000
#define RT305X_ROM_BASE 0x00400000
#define RT305X_FLASH1_BASE 0x1b000000
#define RT305X_FLASH0_BASE 0x1f000000
#define RT305X_SYSC_SIZE 0x100
#define RT305X_TIMER_SIZE 0x100
#define RT305X_INTC_SIZE 0x100
#define RT305X_MEMC_SIZE 0x100
#define RT305X_UART0_SIZE 0x100
#define RT305X_PIO_SIZE 0x100
#define RT305X_UART1_SIZE 0x100
#define RT305X_SPI_SIZE 0x100
#define RT305X_FLASH1_SIZE (16 * 1024 * 1024)
#define RT305X_FLASH0_SIZE (8 * 1024 * 1024)
#define RT3352_EHCI_BASE 0x101c0000
#define RT3352_EHCI_SIZE 0x1000
#define RT3352_OHCI_BASE 0x101c1000
#define RT3352_OHCI_SIZE 0x1000
/* SYSC registers */
#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */
#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
#define RT3352_SYSC_REG_SYSCFG1 0x014
#define RT3352_SYSC_REG_CLKCFG1 0x030
#define RT3352_SYSC_REG_RSTCTRL 0x034
#define RT3352_SYSC_REG_USB_PS 0x05c
#define RT3052_CHIP_NAME0 0x30335452
#define RT3052_CHIP_NAME1 0x20203235
#define RT3350_CHIP_NAME0 0x33335452
#define RT3350_CHIP_NAME1 0x20203035
#define RT3352_CHIP_NAME0 0x33335452
#define RT3352_CHIP_NAME1 0x20203235
#define RT5350_CHIP_NAME0 0x33355452
#define RT5350_CHIP_NAME1 0x20203035
#define CHIP_ID_ID_MASK 0xff
#define CHIP_ID_ID_SHIFT 8
#define CHIP_ID_REV_MASK 0xff
#define RT305X_SYSCFG_CPUCLK_SHIFT 18
#define RT305X_SYSCFG_CPUCLK_MASK 0x1
#define RT305X_SYSCFG_CPUCLK_LOW 0x0
#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
#define RT305X_SYSCFG_SRAM_CS0_MODE_MASK 0x3
#define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL 0
#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1
#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2
#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
#define RT5350_SYSCFG0_CPUCLK_360 0x0
#define RT5350_SYSCFG0_CPUCLK_320 0x2
#define RT5350_SYSCFG0_CPUCLK_300 0x3
#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
#define RT5350_SYSCFG0_DRAM_SIZE_8M 1
#define RT5350_SYSCFG0_DRAM_SIZE_16M 2
#define RT5350_SYSCFG0_DRAM_SIZE_32M 3
#define RT5350_SYSCFG0_DRAM_SIZE_64M 4
#define RT3352_SYSCFG0_XTAL_SEL BIT(20)
#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
#define RT305X_GPIO_MODE_I2C BIT(0)
#define RT305X_GPIO_MODE_SPI BIT(1)
#define RT305X_GPIO_MODE_UART0_SHIFT 2
#define RT305X_GPIO_MODE_UART0_MASK 0x7
#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
#define RT305X_GPIO_MODE_UARTF 0x0
#define RT305X_GPIO_MODE_PCM_UARTF 0x1
#define RT305X_GPIO_MODE_PCM_I2S 0x2
#define RT305X_GPIO_MODE_I2S_UARTF 0x3
#define RT305X_GPIO_MODE_PCM_GPIO 0x4
#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
#define RT305X_GPIO_MODE_GPIO_I2S 0x6
#define RT305X_GPIO_MODE_GPIO 0x7
#define RT305X_GPIO_MODE_UART1 BIT(5)
#define RT305X_GPIO_MODE_JTAG BIT(6)
#define RT305X_GPIO_MODE_MDIO BIT(7)
#define RT305X_GPIO_MODE_SDRAM BIT(8)
#define RT305X_GPIO_MODE_RGMII BIT(9)
#define RT305X_RESET_SYSTEM BIT(0)
#define RT305X_RESET_TIMER BIT(8)
#define RT305X_RESET_INTC BIT(9)
#define RT305X_RESET_MEMC BIT(10)
#define RT305X_RESET_PCM BIT(11)
#define RT305X_RESET_UART0 BIT(12)
#define RT305X_RESET_PIO BIT(13)
#define RT305X_RESET_DMA BIT(14)
#define RT305X_RESET_I2C BIT(16)
#define RT305X_RESET_I2S BIT(17)
#define RT305X_RESET_SPI BIT(18)
#define RT305X_RESET_UART1 BIT(19)
#define RT305X_RESET_WNIC BIT(20)
#define RT305X_RESET_FE BIT(21)
#define RT305X_RESET_OTG BIT(22)
#define RT305X_RESET_ESW BIT(23)
#define RT3352_RSTCTRL_SYS BIT(0)
#define RT3352_RSTCTRL_TIMER BIT(8)
#define RT3352_RSTCTRL_INTC BIT(9)
#define RT3352_RSTCTRL_MEMC BIT(10)
#define RT3352_RSTCTRL_PCM BIT(11)
#define RT3352_RSTCTRL_UART0 BIT(12)
#define RT3352_RSTCTRL_PIO BIT(13)
#define RT3352_RSTCTRL_DMA BIT(14)
#define RT3352_RSTCTRL_I2C BIT(16)
#define RT3352_RSTCTRL_I2S BIT(17)
#define RT3352_RSTCTRL_SPI BIT(18)
#define RT3352_RSTCTRL_UART1 BIT(19)
#define RT3352_RSTCTRL_WNIC BIT(20)
#define RT3352_RSTCTRL_FE BIT(21)
#define RT3352_RSTCTRL_UHST BIT(22)
#define RT3352_RSTCTRL_ESW BIT(23)
#define RT3352_RSTCTRL_EPHY BIT(24)
#define RT3352_RSTCTRL_UDEV BIT(25)
#define RT305X_INTC_INT_SYSCTL BIT(0)
#define RT305X_INTC_INT_TIMER0 BIT(1)
#define RT305X_INTC_INT_TIMER1 BIT(2)
#define RT305X_INTC_INT_IA BIT(3)
#define RT305X_INTC_INT_PCM BIT(4)
#define RT305X_INTC_INT_UART0 BIT(5)
#define RT305X_INTC_INT_PIO BIT(6)
#define RT305X_INTC_INT_DMA BIT(7)
#define RT305X_INTC_INT_NAND BIT(8)
#define RT305X_INTC_INT_PERFC BIT(9)
#define RT305X_INTC_INT_I2S BIT(10)
#define RT305X_INTC_INT_UART1 BIT(12)
#define RT305X_INTC_INT_ESW BIT(17)
#define RT305X_INTC_INT_OTG BIT(18)
#define RT305X_INTC_INT_GLOBAL BIT(31)
/* MEMC registers */
#define MEMC_REG_SDRAM_CFG0 0x00
#define MEMC_REG_SDRAM_CFG1 0x04
#define MEMC_REG_FLASH_CFG0 0x08
#define MEMC_REG_FLASH_CFG1 0x0c
#define MEMC_REG_IA_ADDR 0x10
#define MEMC_REG_IA_TYPE 0x14
#define FLASH_CFG_WIDTH_SHIFT 26
#define FLASH_CFG_WIDTH_MASK 0x3
#define FLASH_CFG_WIDTH_8BIT 0x0
#define FLASH_CFG_WIDTH_16BIT 0x1
#define FLASH_CFG_WIDTH_32BIT 0x2
/* UART registers */
#define UART_REG_RX 0
#define UART_REG_TX 1
#define UART_REG_IER 2
#define UART_REG_IIR 3
#define UART_REG_FCR 4
#define UART_REG_LCR 5
#define UART_REG_MCR 6
#define UART_REG_LSR 7
#endif /* _RT305X_REGS_H_ */

152
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883.h
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@@ -1,152 +0,0 @@
/*
* Ralink RT3662/RT3883 SoC specific definitions
*
* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
*
* Parts of this file are based on Ralink's 2.6.21 BSP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RT3883_H_
#define _RT3883_H_
#include <linux/init.h>
#include <linux/io.h>
#define RT3883_MEM_SIZE_MIN (2 * 1024 * 1024)
#define RT3883_MEM_SIZE_MAX (256 * 1024 * 1024)
#define RT3883_CPU_IRQ_BASE 0
#define RT3883_CPU_IRQ_COUNT 8
#define RT3883_INTC_IRQ_BASE (RT3883_CPU_IRQ_BASE + RT3883_CPU_IRQ_COUNT)
#define RT3883_INTC_IRQ_COUNT 32
#define RT3883_GPIO_IRQ_BASE (RT3883_INTC_IRQ_BASE + RT3883_INTC_IRQ_COUNT)
#define RT3883_GPIO_IRQ_COUNT 96
#define RT3883_PCI_IRQ_BASE (RT3883_GPIO_IRQ_BASE + RT3883_GPIO_IRQ_COUNT)
#define RT3883_PCI_IRQ_COUNT 3
#define RT3883_CPU_IRQ_INTC (RT3883_CPU_IRQ_BASE + 2)
#define RT3883_CPU_IRQ_PCI (RT3883_CPU_IRQ_BASE + 4)
#define RT3883_CPU_IRQ_FE (RT3883_CPU_IRQ_BASE + 5)
#define RT3883_CPU_IRQ_WLAN (RT3883_CPU_IRQ_BASE + 6)
#define RT3883_CPU_IRQ_COUNTER (RT3883_CPU_IRQ_BASE + 7)
#define RT3883_INTC_IRQ_SYSCTL (RT3883_INTC_IRQ_BASE + 0)
#define RT3883_INTC_IRQ_TIMER0 (RT3883_INTC_IRQ_BASE + 1)
#define RT3883_INTC_IRQ_TIMER1 (RT3883_INTC_IRQ_BASE + 2)
#define RT3883_INTC_IRQ_IA (RT3883_INTC_IRQ_BASE + 3)
#define RT3883_INTC_IRQ_PCM (RT3883_INTC_IRQ_BASE + 4)
#define RT3883_INTC_IRQ_UART0 (RT3883_INTC_IRQ_BASE + 5)
#define RT3883_INTC_IRQ_PIO (RT3883_INTC_IRQ_BASE + 6)
#define RT3883_INTC_IRQ_DMA (RT3883_INTC_IRQ_BASE + 7)
#define RT3883_INTC_IRQ_NAND (RT3883_INTC_IRQ_BASE + 8)
#define RT3883_INTC_IRQ_PERFC (RT3883_INTC_IRQ_BASE + 9)
#define RT3883_INTC_IRQ_I2S (RT3883_INTC_IRQ_BASE + 10)
#define RT3883_INTC_IRQ_UART1 (RT3883_INTC_IRQ_BASE + 12)
#define RT3883_INTC_IRQ_UHST (RT3883_INTC_IRQ_BASE + 18)
#define RT3883_INTC_IRQ_UDEV (RT3883_INTC_IRQ_BASE + 19)
#define RT3883_PCI_IRQ_PCI0 (RT3883_PCI_IRQ_BASE + 0)
#define RT3883_PCI_IRQ_PCI1 (RT3883_PCI_IRQ_BASE + 1)
#define RT3883_PCI_IRQ_PCIE (RT3883_PCI_IRQ_BASE + 2)
extern void __iomem *rt3883_sysc_base;
extern void __iomem *rt3883_memc_base;
static inline void rt3883_sysc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt3883_sysc_base + reg);
}
static inline u32 rt3883_sysc_rr(unsigned reg)
{
return __raw_readl(rt3883_sysc_base + reg);
}
static inline void rt3883_memc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt3883_memc_base + reg);
}
static inline u32 rt3883_memc_rr(unsigned reg)
{
return __raw_readl(rt3883_memc_base + reg);
}
#define RT3883_GPIO_I2C_SD 1
#define RT3883_GPIO_I2C_SCLK 2
#define RT3883_GPIO_SPI_CS0 3
#define RT3883_GPIO_SPI_CLK 4
#define RT3883_GPIO_SPI_MOSI 5
#define RT3883_GPIO_SPI_MISO 6
/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
#define RT3883_GPIO_7 7
#define RT3883_GPIO_8 8
#define RT3883_GPIO_9 9
#define RT3883_GPIO_10 10
#define RT3883_GPIO_11 11
#define RT3883_GPIO_12 12
#define RT3883_GPIO_13 13
#define RT3883_GPIO_14 14
#define RT3883_GPIO_UART1_TXD 15
#define RT3883_GPIO_UART1_RXD 16
#define RT3883_GPIO_JTAG_TDO 17
#define RT3883_GPIO_JTAG_TDI 18
#define RT3883_GPIO_JTAG_TMS 19
#define RT3883_GPIO_JTAG_TCLK 20
#define RT3883_GPIO_JTAG_TRST_N 21
#define RT3883_GPIO_MDIO_MDC 22
#define RT3883_GPIO_MDIO_MDIO 23
#define RT3883_GPIO_LNA_PE_A0 32
#define RT3883_GPIO_LNA_PE_A1 33
#define RT3883_GPIO_LNA_PE_A2 34
#define RT3883_GPIO_LNA_PE_G0 35
#define RT3883_GPIO_LNA_PE_G1 36
#define RT3883_GPIO_LNA_PE_G2 37
#define RT3883_GPIO_PCI_AD0 40
#define RT3883_GPIO_PCI_AD31 71
#define RT3883_GPIO_GE2_TXD0 72
#define RT3883_GPIO_GE2_TXD1 73
#define RT3883_GPIO_GE2_TXD2 74
#define RT3883_GPIO_GE2_TXD3 75
#define RT3883_GPIO_GE2_TXEN 76
#define RT3883_GPIO_GE2_TXCLK 77
#define RT3883_GPIO_GE2_RXD0 78
#define RT3883_GPIO_GE2_RXD1 79
#define RT3883_GPIO_GE2_RXD2 80
#define RT3883_GPIO_GE2_RXD3 81
#define RT3883_GPIO_GE2_RXDV 82
#define RT3883_GPIO_GE2_RXCLK 83
#define RT3883_GPIO_GE1_TXD0 84
#define RT3883_GPIO_GE1_TXD1 85
#define RT3883_GPIO_GE1_TXD2 86
#define RT3883_GPIO_GE1_TXD3 87
#define RT3883_GPIO_GE1_TXEN 88
#define RT3883_GPIO_GE1_TXCLK 89
#define RT3883_GPIO_GE1_RXD0 90
#define RT3883_GPIO_GE1_RXD1 91
#define RT3883_GPIO_GE1_RXD2 92
#define RT3883_GPIO_GE1_RXD3 93
#define RT3883_GPIO_GE1_RXDV 94
#define RT3883_GPIO_GE1_RXCLK 95
void rt3883_gpio_init(u32 mode);
#define RT3883_PCI_MODE_PCI 0x01
#define RT3883_PCI_MODE_PCIE 0x02
#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
struct pci_dev;
#ifdef CONFIG_PCI
void rt3883_pci_init(unsigned mode);
void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *));
#else
static inline void rt3883_pci_init(unsigned mode) {}
static inline void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *)) {}
#endif /* CONFIG_PCI */
#endif /* _RT3883_H_ */

55
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
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/*
* Ralink RT3662/RT3883 specific CPU feature overrides
*
* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_sb1_cache 0
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_prefetch 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 1
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 1
#define cpu_has_mipsmt 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */

16
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/irq.h
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/*
* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_RALINK_RT3883_IRQ_H
#define __ASM_MACH_RALINK_RT3883_IRQ_H
#define MIPS_CPU_IRQ_BASE 0
#define NR_IRQS 140
#include_next <irq.h>
#endif /* __ASM_MACH_RALINK_RT3883_IRQ_H */

207
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_regs.h
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/*
* Ralink RT3662/RT3883 SoC register definitions
*
* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RT3883_REGS_H_
#define _RT3883_REGS_H_
#include <linux/bitops.h>
#define RT3883_SDRAM_BASE 0x00000000
#define RT3883_SYSC_BASE 0x10000000
#define RT3883_TIMER_BASE 0x10000100
#define RT3883_INTC_BASE 0x10000200
#define RT3883_MEMC_BASE 0x10000300
#define RT3883_UART0_BASE 0x10000500
#define RT3883_PIO_BASE 0x10000600
#define RT3883_FSCC_BASE 0x10000700
#define RT3883_NANDC_BASE 0x10000810
#define RT3883_I2C_BASE 0x10000900
#define RT3883_I2S_BASE 0x10000a00
#define RT3883_SPI_BASE 0x10000b00
#define RT3883_UART1_BASE 0x10000c00
#define RT3883_PCM_BASE 0x10002000
#define RT3883_GDMA_BASE 0x10002800
#define RT3883_CODEC1_BASE 0x10003000
#define RT3883_CODEC2_BASE 0x10003800
#define RT3883_FE_BASE 0x10100000
#define RT3883_ROM_BASE 0x10118000
#define RT3883_USBDEV_BASE 0x10112000
#define RT3883_PCI_BASE 0x10140000
#define RT3883_WLAN_BASE 0x10180000
#define RT3883_USBHOST_BASE 0x101c0000
#define RT3883_BOOT_BASE 0x1c000000
#define RT3883_SRAM_BASE 0x1e000000
#define RT3883_PCIMEM_BASE 0x20000000
#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
#define RT3883_SYSC_SIZE 0x100
#define RT3883_TIMER_SIZE 0x100
#define RT3883_INTC_SIZE 0x100
#define RT3883_MEMC_SIZE 0x100
#define RT3883_UART0_SIZE 0x100
#define RT3883_UART1_SIZE 0x100
#define RT3883_PIO_SIZE 0x100
#define RT3883_FSCC_SIZE 0x100
#define RT3883_NANDC_SIZE 0x0f0
#define RT3883_I2C_SIZE 0x100
#define RT3883_I2S_SIZE 0x100
#define RT3883_SPI_SIZE 0x100
#define RT3883_PCM_SIZE 0x800
#define RT3883_GDMA_SIZE 0x800
#define RT3883_CODEC1_SIZE 0x800
#define RT3883_CODEC2_SIZE 0x800
#define RT3883_FE_SIZE 0x10000
#define RT3883_ROM_SIZE 0x4000
#define RT3883_USBDEV_SIZE 0x4000
#define RT3883_PCI_SIZE 0x40000
#define RT3883_WLAN_SIZE 0x40000
#define RT3883_USBHOST_SIZE 0x40000
#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
/* SYSC registers */
#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
#define RT3883_SYSC_REG_PMU 0x88
#define RT3883_SYSC_REG_PMU1 0x8c
#define RT3883_REVID_VER_ID_MASK 0x0f
#define RT3883_REVID_VER_ID_SHIFT 8
#define RT3883_REVID_ECO_ID_MASK 0x0f
#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
#define RT3883_SYSCFG0_CPUCLK_250 0x0
#define RT3883_SYSCFG0_CPUCLK_384 0x1
#define RT3883_SYSCFG0_CPUCLK_480 0x2
#define RT3883_SYSCFG0_CPUCLK_500 0x3
#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
#define RT3883_GPIO_MODE_I2C BIT(0)
#define RT3883_GPIO_MODE_SPI BIT(1)
#define RT3883_GPIO_MODE_UART0_SHIFT 2
#define RT3883_GPIO_MODE_UART0_MASK 0x7
#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
#define RT3883_GPIO_MODE_UARTF 0x0
#define RT3883_GPIO_MODE_PCM_UARTF 0x1
#define RT3883_GPIO_MODE_PCM_I2S 0x2
#define RT3883_GPIO_MODE_I2S_UARTF 0x3
#define RT3883_GPIO_MODE_PCM_GPIO 0x4
#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
#define RT3883_GPIO_MODE_GPIO_I2S 0x6
#define RT3883_GPIO_MODE_GPIO 0x7
#define RT3883_GPIO_MODE_UART1 BIT(5)
#define RT3883_GPIO_MODE_JTAG BIT(6)
#define RT3883_GPIO_MODE_MDIO BIT(7)
#define RT3883_GPIO_MODE_GE1 BIT(9)
#define RT3883_GPIO_MODE_GE2 BIT(10)
#define RT3883_GPIO_MODE_PCI_SHIFT 11
#define RT3883_GPIO_MODE_PCI_MASK 0x7
#define RT3883_GPIO_MODE_PCI(_x) ((_x) << RT3883_GPIO_MODE_PCI_SHIFT)
#define RT3883_GPIO_MODE_PCI_DEV 0
#define RT3883_GPIO_MODE_PCI_HOST2 1
#define RT3883_GPIO_MODE_PCI_HOST1 2
#define RT3883_GPIO_MODE_PCI_FNC 3
#define RT3883_GPIO_MODE_PCI_GPIO 7
#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
#define RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
#define RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
#define RT3883_RSTCTRL_FLASH BIT(26)
#define RT3883_RSTCTRL_UDEV BIT(25)
#define RT3883_RSTCTRL_PCI BIT(24)
#define RT3883_RSTCTRL_PCIE BIT(23)
#define RT3883_RSTCTRL_UHST BIT(22)
#define RT3883_RSTCTRL_FE BIT(21)
#define RT3883_RSTCTRL_WLAN BIT(20)
#define RT3883_RSTCTRL_UART1 BIT(29)
#define RT3883_RSTCTRL_SPI BIT(18)
#define RT3883_RSTCTRL_I2S BIT(17)
#define RT3883_RSTCTRL_I2C BIT(16)
#define RT3883_RSTCTRL_NAND BIT(15)
#define RT3883_RSTCTRL_DMA BIT(14)
#define RT3883_RSTCTRL_PIO BIT(13)
#define RT3883_RSTCTRL_UART BIT(12)
#define RT3883_RSTCTRL_PCM BIT(11)
#define RT3883_RSTCTRL_MC BIT(10)
#define RT3883_RSTCTRL_INTC BIT(9)
#define RT3883_RSTCTRL_TIMER BIT(8)
#define RT3883_RSTCTRL_SYS BIT(0)
#define RT3883_INTC_INT_SYSCTL BIT(0)
#define RT3883_INTC_INT_TIMER0 BIT(1)
#define RT3883_INTC_INT_TIMER1 BIT(2)
#define RT3883_INTC_INT_IA BIT(3)
#define RT3883_INTC_INT_PCM BIT(4)
#define RT3883_INTC_INT_UART0 BIT(5)
#define RT3883_INTC_INT_PIO BIT(6)
#define RT3883_INTC_INT_DMA BIT(7)
#define RT3883_INTC_INT_NAND BIT(8)
#define RT3883_INTC_INT_PERFC BIT(9)
#define RT3883_INTC_INT_I2S BIT(10)
#define RT3883_INTC_INT_UART1 BIT(12)
#define RT3883_INTC_INT_UHST BIT(18)
#define RT3883_INTC_INT_UDEV BIT(19)
/* FLASH/SRAM/Codec Controller registers */
#define RT3883_FSCC_REG_FLASH_CFG0 0x00
#define RT3883_FSCC_REG_FLASH_CFG1 0x04
#define RT3883_FSCC_REG_CODEC_CFG0 0x40
#define RT3883_FSCC_REG_CODEC_CFG1 0x44
#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
/* UART registers */
#define RT3883_UART_REG_RX 0
#define RT3883_UART_REG_TX 1
#define RT3883_UART_REG_IER 2
#define RT3883_UART_REG_IIR 3
#define RT3883_UART_REG_FCR 4
#define RT3883_UART_REG_LCR 5
#define RT3883_UART_REG_MCR 6
#define RT3883_UART_REG_LSR 7
#endif /* _RT3883_REGS_H_ */

25
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/war.h
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@@ -1,25 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MACH_RALINK_WAR_H
#define __ASM_MACH_RALINK_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define RM9000_CDEX_SMP_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MACH_RALINK_WAR_H */