forked from Ivasoft/openwrt
uboot-rockchip: update NanoPi R2S patches
Update the patches required for the NanoPi R2S to match the DTS accepted for upstream Linux. The U-Boot patch meanwhile is still pending upstream. Signed-off-by: David Bauer <mail@david-bauer.net>
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@@ -19,7 +19,7 @@ U_BOOT_DEVICE(syscon_at_ff100000) = {
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static const struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
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.reg = {0xff440000, 0x1000},
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.rockchip_grf = 0x3a,
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.rockchip_grf = 0x3b,
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};
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U_BOOT_DEVICE(clock_controller_at_ff440000) = {
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.name = "rockchip_rk3328_cru",
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@@ -49,7 +49,6 @@ U_BOOT_DEVICE(serial_at_ff130000) = {
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static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = {
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.bus_width = 0x4,
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.cap_mmc_highspeed = true,
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.cap_sd_highspeed = true,
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.clocks = {
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{&dtv_clock_controller_at_ff440000, {317}},
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@@ -60,11 +59,15 @@ static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = {
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.fifo_depth = 0x100,
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.interrupts = {0x0, 0xc, 0x4},
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.max_frequency = 0x8f0d180,
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.pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
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.pinctrl_0 = {0x48, 0x49, 0x4a, 0x4b},
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.pinctrl_names = "default",
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.reg = {0xff500000, 0x4000},
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.sd_uhs_sdr104 = true,
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.sd_uhs_sdr12 = true,
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.sd_uhs_sdr25 = true,
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.sd_uhs_sdr50 = true,
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.u_boot_spl_fifo_mode = true,
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.vmmc_supply = 0x4b,
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.vmmc_supply = 0x4c,
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.vqmmc_supply = 0x1e,
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};
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U_BOOT_DEVICE(mmc_at_ff500000) = {
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@@ -75,7 +78,7 @@ U_BOOT_DEVICE(mmc_at_ff500000) = {
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static const struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = {
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.ranges = true,
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.rockchip_grf = 0x3a,
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.rockchip_grf = 0x3b,
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};
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U_BOOT_DEVICE(pinctrl) = {
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.name = "rockchip_rk3328_pinctrl",
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@@ -98,9 +101,10 @@ U_BOOT_DEVICE(gpio0_at_ff210000) = {
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};
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static const struct dtd_regulator_fixed dtv_sdmmc_regulator = {
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.gpio = {0x60, 0x1e, 0x1},
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.pinctrl_0 = 0x61,
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.gpio = {0x61, 0x1e, 0x1},
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.pinctrl_0 = 0x68,
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.pinctrl_names = "default",
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.regulator_boot_on = true,
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.regulator_max_microvolt = 0x325aa0,
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.regulator_min_microvolt = 0x325aa0,
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.regulator_name = "vcc_sd",
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@@ -10,6 +10,7 @@ struct dtd_regulator_fixed {
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fdt32_t gpio[3];
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fdt32_t pinctrl_0;
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const char * pinctrl_names;
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bool regulator_boot_on;
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fdt32_t regulator_max_microvolt;
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fdt32_t regulator_min_microvolt;
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const char * regulator_name;
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@@ -32,7 +33,6 @@ struct dtd_rockchip_rk3328_dmc {
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};
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struct dtd_rockchip_rk3328_dw_mshc {
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fdt32_t bus_width;
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bool cap_mmc_highspeed;
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bool cap_sd_highspeed;
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struct phandle_1_arg clocks[4];
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bool disable_wp;
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@@ -42,6 +42,10 @@ struct dtd_rockchip_rk3328_dw_mshc {
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fdt32_t pinctrl_0[4];
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const char * pinctrl_names;
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fdt64_t reg[2];
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bool sd_uhs_sdr104;
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bool sd_uhs_sdr12;
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bool sd_uhs_sdr25;
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bool sd_uhs_sdr50;
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bool u_boot_spl_fifo_mode;
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fdt32_t vmmc_supply;
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fdt32_t vqmmc_supply;
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