forked from Ivasoft/openwrt
ipq40xx: remove support for kernel 4.19
The target uses 5.4 as default kernel since 03/2020. Kernel 4.19 support is not really maintained anymore, it does not seem to be needed, and removing it will make upcoming driver updates easier. Thus, remove it. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This commit is contained in:
Adrian Schmutzler
@@ -0,0 +1,9 @@
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#
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## Makefile for the Qualcomm Atheros ethernet edma driver
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#
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obj-$(CONFIG_ESSEDMA) += essedma.o
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essedma-objs := edma_axi.o edma.o edma_ethtool.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,455 @@
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/*
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* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all copies.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
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* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _EDMA_H_
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#define _EDMA_H_
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/io.h>
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#include <linux/vmalloc.h>
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#include <linux/pagemap.h>
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#include <linux/smp.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/sysctl.h>
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#include <linux/phy.h>
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#include <linux/of_net.h>
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#include <net/checksum.h>
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#include <net/ip6_checksum.h>
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#include <asm-generic/bug.h>
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#include "ess_edma.h"
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#define EDMA_CPU_CORES_SUPPORTED 4
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#define EDMA_MAX_PORTID_SUPPORTED 5
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#define EDMA_MAX_VLAN_SUPPORTED EDMA_MAX_PORTID_SUPPORTED
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#define EDMA_MAX_PORTID_BITMAP_INDEX (EDMA_MAX_PORTID_SUPPORTED + 1)
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#define EDMA_MAX_PORTID_BITMAP_SUPPORTED 0x1f /* 0001_1111 = 0x1f */
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#define EDMA_MAX_NETDEV_PER_QUEUE 4 /* 3 Netdev per queue, 1 space for indexing */
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#define EDMA_MAX_RECEIVE_QUEUE 8
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#define EDMA_MAX_TRANSMIT_QUEUE 16
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/* WAN/LAN adapter number */
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#define EDMA_WAN 0
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#define EDMA_LAN 1
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/* VLAN tag */
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#define EDMA_LAN_DEFAULT_VLAN 1
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#define EDMA_WAN_DEFAULT_VLAN 2
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#define EDMA_DEFAULT_GROUP1_VLAN 1
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#define EDMA_DEFAULT_GROUP2_VLAN 2
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#define EDMA_DEFAULT_GROUP3_VLAN 3
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#define EDMA_DEFAULT_GROUP4_VLAN 4
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#define EDMA_DEFAULT_GROUP5_VLAN 5
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/* Queues exposed to linux kernel */
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#define EDMA_NETDEV_TX_QUEUE 4
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#define EDMA_NETDEV_RX_QUEUE 4
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/* Number of queues per core */
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#define EDMA_NUM_TXQ_PER_CORE 4
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#define EDMA_NUM_RXQ_PER_CORE 2
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#define EDMA_TPD_EOP_SHIFT 31
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#define EDMA_PORT_ID_SHIFT 12
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#define EDMA_PORT_ID_MASK 0x7
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/* tpd word 3 bit 18-28 */
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#define EDMA_TPD_PORT_BITMAP_SHIFT 18
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#define EDMA_TPD_FROM_CPU_SHIFT 25
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#define EDMA_FROM_CPU_MASK 0x80
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#define EDMA_SKB_PRIORITY_MASK 0x38
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/* TX/RX descriptor ring count */
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/* should be a power of 2 */
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#define EDMA_RX_RING_SIZE 128
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#define EDMA_TX_RING_SIZE 128
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/* Flags used in paged/non paged mode */
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#define EDMA_RX_HEAD_BUFF_SIZE_JUMBO 256
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#define EDMA_RX_HEAD_BUFF_SIZE 1540
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/* MAX frame size supported by switch */
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#define EDMA_MAX_JUMBO_FRAME_SIZE 9216
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/* Configurations */
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#define EDMA_INTR_CLEAR_TYPE 0
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#define EDMA_INTR_SW_IDX_W_TYPE 0
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#define EDMA_FIFO_THRESH_TYPE 0
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#define EDMA_RSS_TYPE 0
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#define EDMA_RX_IMT 0x0020
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#define EDMA_TX_IMT 0x0050
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#define EDMA_TPD_BURST 5
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#define EDMA_TXF_BURST 0x100
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#define EDMA_RFD_BURST 8
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#define EDMA_RFD_THR 16
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#define EDMA_RFD_LTHR 0
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/* RX/TX per CPU based mask/shift */
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#define EDMA_TX_PER_CPU_MASK 0xF
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#define EDMA_RX_PER_CPU_MASK 0x3
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#define EDMA_TX_PER_CPU_MASK_SHIFT 0x2
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#define EDMA_RX_PER_CPU_MASK_SHIFT 0x1
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#define EDMA_TX_CPU_START_SHIFT 0x2
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#define EDMA_RX_CPU_START_SHIFT 0x1
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/* FLags used in transmit direction */
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#define EDMA_HW_CHECKSUM 0x00000001
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#define EDMA_VLAN_TX_TAG_INSERT_FLAG 0x00000002
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#define EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG 0x00000004
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#define EDMA_SW_DESC_FLAG_LAST 0x1
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#define EDMA_SW_DESC_FLAG_SKB_HEAD 0x2
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#define EDMA_SW_DESC_FLAG_SKB_FRAG 0x4
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#define EDMA_SW_DESC_FLAG_SKB_FRAGLIST 0x8
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#define EDMA_SW_DESC_FLAG_SKB_NONE 0x10
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#define EDMA_SW_DESC_FLAG_SKB_REUSE 0x20
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#define EDMA_MAX_SKB_FRAGS (MAX_SKB_FRAGS + 1)
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/* Ethtool specific list of EDMA supported features */
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#define EDMA_SUPPORTED_FEATURES (SUPPORTED_10baseT_Half \
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| SUPPORTED_10baseT_Full \
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| SUPPORTED_100baseT_Half \
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| SUPPORTED_100baseT_Full \
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| SUPPORTED_1000baseT_Full)
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/* Recevie side atheros Header */
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#define EDMA_RX_ATH_HDR_VERSION 0x2
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#define EDMA_RX_ATH_HDR_VERSION_SHIFT 14
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#define EDMA_RX_ATH_HDR_PRIORITY_SHIFT 11
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#define EDMA_RX_ATH_PORT_TYPE_SHIFT 6
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#define EDMA_RX_ATH_HDR_RSTP_PORT_TYPE 0x4
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/* Transmit side atheros Header */
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#define EDMA_TX_ATH_HDR_PORT_BITMAP_MASK 0x7F
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#define EDMA_TX_ATH_HDR_FROM_CPU_MASK 0x80
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#define EDMA_TX_ATH_HDR_FROM_CPU_SHIFT 7
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#define EDMA_TXQ_START_CORE0 8
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#define EDMA_TXQ_START_CORE1 12
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#define EDMA_TXQ_START_CORE2 0
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#define EDMA_TXQ_START_CORE3 4
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#define EDMA_TXQ_IRQ_MASK_CORE0 0x0F00
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#define EDMA_TXQ_IRQ_MASK_CORE1 0xF000
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#define EDMA_TXQ_IRQ_MASK_CORE2 0x000F
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#define EDMA_TXQ_IRQ_MASK_CORE3 0x00F0
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#define EDMA_ETH_HDR_LEN 12
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#define EDMA_ETH_TYPE_MASK 0xFFFF
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#define EDMA_RX_BUFFER_WRITE 16
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#define EDMA_RFD_AVAIL_THR 80
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#define EDMA_GMAC_NO_MDIO_PHY PHY_MAX_ADDR
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extern int ssdk_rfs_ipct_rule_set(__be32 ip_src, __be32 ip_dst,
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__be16 sport, __be16 dport,
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uint8_t proto, u16 loadbalance, bool action);
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struct edma_ethtool_statistics {
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u32 tx_q0_pkt;
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u32 tx_q1_pkt;
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u32 tx_q2_pkt;
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u32 tx_q3_pkt;
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u32 tx_q4_pkt;
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u32 tx_q5_pkt;
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u32 tx_q6_pkt;
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u32 tx_q7_pkt;
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u32 tx_q8_pkt;
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u32 tx_q9_pkt;
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u32 tx_q10_pkt;
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u32 tx_q11_pkt;
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u32 tx_q12_pkt;
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u32 tx_q13_pkt;
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u32 tx_q14_pkt;
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u32 tx_q15_pkt;
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u32 tx_q0_byte;
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u32 tx_q1_byte;
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u32 tx_q2_byte;
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u32 tx_q3_byte;
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u32 tx_q4_byte;
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u32 tx_q5_byte;
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u32 tx_q6_byte;
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u32 tx_q7_byte;
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u32 tx_q8_byte;
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u32 tx_q9_byte;
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u32 tx_q10_byte;
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u32 tx_q11_byte;
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u32 tx_q12_byte;
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u32 tx_q13_byte;
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u32 tx_q14_byte;
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u32 tx_q15_byte;
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u32 rx_q0_pkt;
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u32 rx_q1_pkt;
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u32 rx_q2_pkt;
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u32 rx_q3_pkt;
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u32 rx_q4_pkt;
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u32 rx_q5_pkt;
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u32 rx_q6_pkt;
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u32 rx_q7_pkt;
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u32 rx_q0_byte;
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u32 rx_q1_byte;
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u32 rx_q2_byte;
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u32 rx_q3_byte;
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u32 rx_q4_byte;
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u32 rx_q5_byte;
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u32 rx_q6_byte;
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u32 rx_q7_byte;
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u32 tx_desc_error;
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u32 rx_alloc_fail_ctr;
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};
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struct edma_mdio_data {
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struct mii_bus *mii_bus;
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void __iomem *membase;
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int phy_irq[PHY_MAX_ADDR];
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};
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/* EDMA LINK state */
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enum edma_link_state {
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__EDMA_LINKUP, /* Indicate link is UP */
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__EDMA_LINKDOWN /* Indicate link is down */
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};
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/* EDMA GMAC state */
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enum edma_gmac_state {
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__EDMA_UP /* use to indicate GMAC is up */
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};
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/* edma transmit descriptor */
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struct edma_tx_desc {
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__le16 len; /* full packet including CRC */
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__le16 svlan_tag; /* vlan tag */
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__le32 word1; /* byte 4-7 */
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__le32 addr; /* address of buffer */
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__le32 word3; /* byte 12 */
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};
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/* edma receive return descriptor */
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struct edma_rx_return_desc {
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u16 rrd0;
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u16 rrd1;
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u16 rrd2;
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u16 rrd3;
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u16 rrd4;
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u16 rrd5;
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u16 rrd6;
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u16 rrd7;
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};
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/* RFD descriptor */
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struct edma_rx_free_desc {
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__le32 buffer_addr; /* buffer address */
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};
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/* edma hw specific data */
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struct edma_hw {
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u32 __iomem *hw_addr; /* inner register address */
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struct edma_adapter *adapter; /* netdevice adapter */
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u32 rx_intr_mask; /*rx interrupt mask */
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u32 tx_intr_mask; /* tx interrupt nask */
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u32 misc_intr_mask; /* misc interrupt mask */
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u32 wol_intr_mask; /* wake on lan interrupt mask */
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bool intr_clear_type; /* interrupt clear */
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bool intr_sw_idx_w; /* interrupt software index */
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u32 rx_head_buff_size; /* Rx buffer size */
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u8 rss_type; /* rss protocol type */
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};
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/* edma_sw_desc stores software descriptor
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* SW descriptor has 1:1 map with HW descriptor
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*/
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struct edma_sw_desc {
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struct sk_buff *skb;
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dma_addr_t dma; /* dma address */
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u16 length; /* Tx/Rx buffer length */
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u32 flags;
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};
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/* per core related information */
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struct edma_per_cpu_queues_info {
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struct napi_struct napi; /* napi associated with the core */
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u32 tx_mask; /* tx interrupt mask */
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u32 rx_mask; /* rx interrupt mask */
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u32 tx_status; /* tx interrupt status */
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u32 rx_status; /* rx interrupt status */
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u32 tx_start; /* tx queue start */
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u32 rx_start; /* rx queue start */
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struct edma_common_info *edma_cinfo; /* edma common info */
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};
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/* edma specific common info */
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struct edma_common_info {
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struct edma_tx_desc_ring *tpd_ring[16]; /* 16 Tx queues */
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struct edma_rfd_desc_ring *rfd_ring[8]; /* 8 Rx queues */
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struct platform_device *pdev; /* device structure */
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struct net_device *netdev[EDMA_MAX_PORTID_SUPPORTED];
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struct net_device *portid_netdev_lookup_tbl[EDMA_MAX_PORTID_BITMAP_INDEX];
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struct ctl_table_header *edma_ctl_table_hdr;
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int num_gmac;
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struct edma_ethtool_statistics edma_ethstats; /* ethtool stats */
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int num_rx_queues; /* number of rx queue */
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u32 num_tx_queues; /* number of tx queue */
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u32 tx_irq[16]; /* number of tx irq */
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u32 rx_irq[8]; /* number of rx irq */
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u32 from_cpu; /* from CPU TPD field */
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u32 num_rxq_per_core; /* Rx queues per core */
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u32 num_txq_per_core; /* Tx queues per core */
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u16 tx_ring_count; /* Tx ring count */
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u16 rx_ring_count; /* Rx ring*/
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u16 rx_head_buffer_len; /* rx buffer length */
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u16 rx_page_buffer_len; /* rx buffer length */
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u32 page_mode; /* Jumbo frame supported flag */
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u32 fraglist_mode; /* fraglist supported flag */
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struct edma_hw hw; /* edma hw specific structure */
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struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
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spinlock_t stats_lock; /* protect edma stats area for updation */
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struct timer_list edma_stats_timer;
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bool is_single_phy;
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void __iomem *ess_hw_addr;
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struct clk *ess_clk;
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};
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/* transimit packet descriptor (tpd) ring */
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struct edma_tx_desc_ring {
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struct netdev_queue *nq[EDMA_MAX_NETDEV_PER_QUEUE]; /* Linux queue index */
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struct net_device *netdev[EDMA_MAX_NETDEV_PER_QUEUE];
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/* Array of netdevs associated with the tpd ring */
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void *hw_desc; /* descriptor ring virtual address */
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struct edma_sw_desc *sw_desc; /* buffer associated with ring */
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int netdev_bmp; /* Bitmap for per-ring netdevs */
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u32 size; /* descriptor ring length in bytes */
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u16 count; /* number of descriptors in the ring */
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dma_addr_t dma; /* descriptor ring physical address */
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u16 sw_next_to_fill; /* next Tx descriptor to fill */
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u16 sw_next_to_clean; /* next Tx descriptor to clean */
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};
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/* receive free descriptor (rfd) ring */
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struct edma_rfd_desc_ring {
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void *hw_desc; /* descriptor ring virtual address */
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struct edma_sw_desc *sw_desc; /* buffer associated with ring */
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u16 size; /* bytes allocated to sw_desc */
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u16 count; /* number of descriptors in the ring */
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dma_addr_t dma; /* descriptor ring physical address */
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u16 sw_next_to_fill; /* next descriptor to fill */
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u16 sw_next_to_clean; /* next descriptor to clean */
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u16 pending_fill; /* fill pending from previous iteration */
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};
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/* edma_rfs_flter_node - rfs filter node in hash table */
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struct edma_rfs_filter_node {
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struct flow_keys keys;
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u32 flow_id; /* flow_id of filter provided by kernel */
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u16 filter_id; /* filter id of filter returned by adaptor */
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u16 rq_id; /* desired rq index */
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struct hlist_node node; /* edma rfs list node */
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};
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/* edma_rfs_flow_tbl - rfs flow table */
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struct edma_rfs_flow_table {
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u16 max_num_filter; /* Maximum number of filters edma supports */
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u16 hashtoclean; /* hash table index to clean next */
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int filter_available; /* Number of free filters available */
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struct hlist_head hlist_head[EDMA_RFS_FLOW_ENTRIES];
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spinlock_t rfs_ftab_lock;
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struct timer_list expire_rfs; /* timer function for edma_rps_may_expire_flow */
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};
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/* EDMA net device structure */
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struct edma_adapter {
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struct net_device *netdev; /* netdevice */
|
||||
struct platform_device *pdev; /* platform device */
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struct edma_common_info *edma_cinfo; /* edma common info */
|
||||
struct phy_device *phydev; /* Phy device */
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struct edma_rfs_flow_table rfs; /* edma rfs flow table */
|
||||
struct net_device_stats stats; /* netdev statistics */
|
||||
set_rfs_filter_callback_t set_rfs_rule;
|
||||
u32 flags;/* status flags */
|
||||
unsigned long state_flags; /* GMAC up/down flags */
|
||||
u32 forced_speed; /* link force speed */
|
||||
u32 forced_duplex; /* link force duplex */
|
||||
u32 link_state; /* phy link state */
|
||||
u32 phy_mdio_addr; /* PHY device address on MII interface */
|
||||
u32 poll_required; /* check if link polling is required */
|
||||
u32 tx_start_offset[CONFIG_NR_CPUS]; /* tx queue start */
|
||||
u32 default_vlan_tag; /* vlan tag */
|
||||
u32 dp_bitmap;
|
||||
uint8_t phy_id[MII_BUS_ID_SIZE + 3];
|
||||
};
|
||||
|
||||
int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo);
|
||||
int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo);
|
||||
int edma_open(struct net_device *netdev);
|
||||
int edma_close(struct net_device *netdev);
|
||||
void edma_free_tx_resources(struct edma_common_info *edma_c_info);
|
||||
void edma_free_rx_resources(struct edma_common_info *edma_c_info);
|
||||
int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo);
|
||||
int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo);
|
||||
void edma_free_tx_rings(struct edma_common_info *edma_cinfo);
|
||||
void edma_free_rx_rings(struct edma_common_info *edma_cinfo);
|
||||
void edma_free_queues(struct edma_common_info *edma_cinfo);
|
||||
void edma_irq_disable(struct edma_common_info *edma_cinfo);
|
||||
int edma_reset(struct edma_common_info *edma_cinfo);
|
||||
int edma_poll(struct napi_struct *napi, int budget);
|
||||
netdev_tx_t edma_xmit(struct sk_buff *skb,
|
||||
struct net_device *netdev);
|
||||
int edma_configure(struct edma_common_info *edma_cinfo);
|
||||
void edma_irq_enable(struct edma_common_info *edma_cinfo);
|
||||
void edma_enable_tx_ctrl(struct edma_hw *hw);
|
||||
void edma_enable_rx_ctrl(struct edma_hw *hw);
|
||||
void edma_stop_rx_tx(struct edma_hw *hw);
|
||||
void edma_free_irqs(struct edma_adapter *adapter);
|
||||
irqreturn_t edma_interrupt(int irq, void *dev);
|
||||
void edma_write_reg(u16 reg_addr, u32 reg_value);
|
||||
void edma_read_reg(u16 reg_addr, volatile u32 *reg_value);
|
||||
struct net_device_stats *edma_get_stats(struct net_device *netdev);
|
||||
int edma_set_mac_addr(struct net_device *netdev, void *p);
|
||||
int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
|
||||
u16 rxq, u32 flow_id);
|
||||
int edma_register_rfs_filter(struct net_device *netdev,
|
||||
set_rfs_filter_callback_t set_filter);
|
||||
void edma_flow_may_expire(struct timer_list *t);
|
||||
void edma_set_ethtool_ops(struct net_device *netdev);
|
||||
void edma_set_stp_rstp(bool tag);
|
||||
void edma_assign_ath_hdr_type(int tag);
|
||||
int edma_get_default_vlan_tag(struct net_device *netdev);
|
||||
void edma_adjust_link(struct net_device *netdev);
|
||||
int edma_fill_netdev(struct edma_common_info *edma_cinfo, int qid, int num, int txq_id);
|
||||
void edma_read_append_stats(struct edma_common_info *edma_cinfo);
|
||||
void edma_change_tx_coalesce(int usecs);
|
||||
void edma_change_rx_coalesce(int usecs);
|
||||
void edma_get_tx_rx_coalesce(u32 *reg_val);
|
||||
void edma_clear_irq_status(void);
|
||||
void ess_set_port_status_speed(struct edma_common_info *edma_cinfo,
|
||||
struct phy_device *phydev, uint8_t port_id);
|
||||
#endif /* _EDMA_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,384 @@
|
||||
/*
|
||||
* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all copies.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/string.h>
|
||||
#include "edma.h"
|
||||
|
||||
struct edma_ethtool_stats {
|
||||
uint8_t stat_string[ETH_GSTRING_LEN];
|
||||
uint32_t stat_offset;
|
||||
};
|
||||
|
||||
#define EDMA_STAT(m) offsetof(struct edma_ethtool_statistics, m)
|
||||
#define DRVINFO_LEN 32
|
||||
|
||||
/* Array of strings describing statistics
|
||||
*/
|
||||
static const struct edma_ethtool_stats edma_gstrings_stats[] = {
|
||||
{"tx_q0_pkt", EDMA_STAT(tx_q0_pkt)},
|
||||
{"tx_q1_pkt", EDMA_STAT(tx_q1_pkt)},
|
||||
{"tx_q2_pkt", EDMA_STAT(tx_q2_pkt)},
|
||||
{"tx_q3_pkt", EDMA_STAT(tx_q3_pkt)},
|
||||
{"tx_q4_pkt", EDMA_STAT(tx_q4_pkt)},
|
||||
{"tx_q5_pkt", EDMA_STAT(tx_q5_pkt)},
|
||||
{"tx_q6_pkt", EDMA_STAT(tx_q6_pkt)},
|
||||
{"tx_q7_pkt", EDMA_STAT(tx_q7_pkt)},
|
||||
{"tx_q8_pkt", EDMA_STAT(tx_q8_pkt)},
|
||||
{"tx_q9_pkt", EDMA_STAT(tx_q9_pkt)},
|
||||
{"tx_q10_pkt", EDMA_STAT(tx_q10_pkt)},
|
||||
{"tx_q11_pkt", EDMA_STAT(tx_q11_pkt)},
|
||||
{"tx_q12_pkt", EDMA_STAT(tx_q12_pkt)},
|
||||
{"tx_q13_pkt", EDMA_STAT(tx_q13_pkt)},
|
||||
{"tx_q14_pkt", EDMA_STAT(tx_q14_pkt)},
|
||||
{"tx_q15_pkt", EDMA_STAT(tx_q15_pkt)},
|
||||
{"tx_q0_byte", EDMA_STAT(tx_q0_byte)},
|
||||
{"tx_q1_byte", EDMA_STAT(tx_q1_byte)},
|
||||
{"tx_q2_byte", EDMA_STAT(tx_q2_byte)},
|
||||
{"tx_q3_byte", EDMA_STAT(tx_q3_byte)},
|
||||
{"tx_q4_byte", EDMA_STAT(tx_q4_byte)},
|
||||
{"tx_q5_byte", EDMA_STAT(tx_q5_byte)},
|
||||
{"tx_q6_byte", EDMA_STAT(tx_q6_byte)},
|
||||
{"tx_q7_byte", EDMA_STAT(tx_q7_byte)},
|
||||
{"tx_q8_byte", EDMA_STAT(tx_q8_byte)},
|
||||
{"tx_q9_byte", EDMA_STAT(tx_q9_byte)},
|
||||
{"tx_q10_byte", EDMA_STAT(tx_q10_byte)},
|
||||
{"tx_q11_byte", EDMA_STAT(tx_q11_byte)},
|
||||
{"tx_q12_byte", EDMA_STAT(tx_q12_byte)},
|
||||
{"tx_q13_byte", EDMA_STAT(tx_q13_byte)},
|
||||
{"tx_q14_byte", EDMA_STAT(tx_q14_byte)},
|
||||
{"tx_q15_byte", EDMA_STAT(tx_q15_byte)},
|
||||
{"rx_q0_pkt", EDMA_STAT(rx_q0_pkt)},
|
||||
{"rx_q1_pkt", EDMA_STAT(rx_q1_pkt)},
|
||||
{"rx_q2_pkt", EDMA_STAT(rx_q2_pkt)},
|
||||
{"rx_q3_pkt", EDMA_STAT(rx_q3_pkt)},
|
||||
{"rx_q4_pkt", EDMA_STAT(rx_q4_pkt)},
|
||||
{"rx_q5_pkt", EDMA_STAT(rx_q5_pkt)},
|
||||
{"rx_q6_pkt", EDMA_STAT(rx_q6_pkt)},
|
||||
{"rx_q7_pkt", EDMA_STAT(rx_q7_pkt)},
|
||||
{"rx_q0_byte", EDMA_STAT(rx_q0_byte)},
|
||||
{"rx_q1_byte", EDMA_STAT(rx_q1_byte)},
|
||||
{"rx_q2_byte", EDMA_STAT(rx_q2_byte)},
|
||||
{"rx_q3_byte", EDMA_STAT(rx_q3_byte)},
|
||||
{"rx_q4_byte", EDMA_STAT(rx_q4_byte)},
|
||||
{"rx_q5_byte", EDMA_STAT(rx_q5_byte)},
|
||||
{"rx_q6_byte", EDMA_STAT(rx_q6_byte)},
|
||||
{"rx_q7_byte", EDMA_STAT(rx_q7_byte)},
|
||||
{"tx_desc_error", EDMA_STAT(tx_desc_error)},
|
||||
{"rx_alloc_fail_ctr", EDMA_STAT(rx_alloc_fail_ctr)},
|
||||
};
|
||||
|
||||
#define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats)
|
||||
|
||||
/* edma_get_strset_count()
|
||||
* Get strset count
|
||||
*/
|
||||
static int edma_get_strset_count(struct net_device *netdev,
|
||||
int sset)
|
||||
{
|
||||
switch (sset) {
|
||||
case ETH_SS_STATS:
|
||||
return EDMA_STATS_LEN;
|
||||
default:
|
||||
netdev_dbg(netdev, "%s: Invalid string set", __func__);
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* edma_get_strings()
|
||||
* get stats string
|
||||
*/
|
||||
static void edma_get_strings(struct net_device *netdev, uint32_t stringset,
|
||||
uint8_t *data)
|
||||
{
|
||||
uint8_t *p = data;
|
||||
uint32_t i;
|
||||
|
||||
switch (stringset) {
|
||||
case ETH_SS_STATS:
|
||||
for (i = 0; i < EDMA_STATS_LEN; i++) {
|
||||
memcpy(p, edma_gstrings_stats[i].stat_string,
|
||||
min((size_t)ETH_GSTRING_LEN,
|
||||
strlen(edma_gstrings_stats[i].stat_string)
|
||||
+ 1));
|
||||
p += ETH_GSTRING_LEN;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* edma_get_ethtool_stats()
|
||||
* Get ethtool statistics
|
||||
*/
|
||||
static void edma_get_ethtool_stats(struct net_device *netdev,
|
||||
struct ethtool_stats *stats, uint64_t *data)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
|
||||
int i;
|
||||
uint8_t *p = NULL;
|
||||
|
||||
edma_read_append_stats(edma_cinfo);
|
||||
|
||||
for(i = 0; i < EDMA_STATS_LEN; i++) {
|
||||
p = (uint8_t *)&(edma_cinfo->edma_ethstats) +
|
||||
edma_gstrings_stats[i].stat_offset;
|
||||
data[i] = *(uint32_t *)p;
|
||||
}
|
||||
}
|
||||
|
||||
/* edma_get_drvinfo()
|
||||
* get edma driver info
|
||||
*/
|
||||
static void edma_get_drvinfo(struct net_device *dev,
|
||||
struct ethtool_drvinfo *info)
|
||||
{
|
||||
strlcpy(info->driver, "ess_edma", DRVINFO_LEN);
|
||||
strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
|
||||
}
|
||||
|
||||
/* edma_nway_reset()
|
||||
* Reset the phy, if available.
|
||||
*/
|
||||
static int edma_nway_reset(struct net_device *netdev)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* edma_get_wol()
|
||||
* get wake on lan info
|
||||
*/
|
||||
static void edma_get_wol(struct net_device *netdev,
|
||||
struct ethtool_wolinfo *wol)
|
||||
{
|
||||
wol->supported = 0;
|
||||
wol->wolopts = 0;
|
||||
}
|
||||
|
||||
/* edma_get_msglevel()
|
||||
* get message level.
|
||||
*/
|
||||
static uint32_t edma_get_msglevel(struct net_device *netdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_settings()
|
||||
* Get edma settings
|
||||
*/
|
||||
static int edma_get_settings(struct net_device *netdev,
|
||||
struct ethtool_link_ksettings *cmd)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
if (adapter->poll_required) {
|
||||
struct phy_device *phydev = NULL;
|
||||
uint16_t phyreg;
|
||||
|
||||
if ((adapter->forced_speed != SPEED_UNKNOWN)
|
||||
&& !(adapter->poll_required))
|
||||
return -EPERM;
|
||||
|
||||
phydev = adapter->phydev;
|
||||
|
||||
linkmode_copy(cmd->link_modes.advertising, phydev->advertising);
|
||||
linkmode_copy(cmd->link_modes.supported, phydev->supported);
|
||||
|
||||
cmd->base.autoneg = phydev->autoneg;
|
||||
|
||||
if (adapter->link_state == __EDMA_LINKDOWN) {
|
||||
cmd->base.speed = SPEED_UNKNOWN;
|
||||
cmd->base.duplex = DUPLEX_UNKNOWN;
|
||||
} else {
|
||||
cmd->base.speed = phydev->speed;
|
||||
cmd->base.duplex = phydev->duplex;
|
||||
}
|
||||
|
||||
cmd->base.phy_address = adapter->phy_mdio_addr;
|
||||
|
||||
phyreg = (uint16_t)phy_read(adapter->phydev, MII_LPA);
|
||||
if (phyreg & LPA_10HALF)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_10FULL)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_100HALF)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_100FULL)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
phyreg = (uint16_t)phy_read(adapter->phydev, MII_STAT1000);
|
||||
if (phyreg & LPA_1000HALF)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_1000FULL)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
} else {
|
||||
/* If the speed/duplex for this GMAC is forced and we
|
||||
* are not polling for link state changes, return the
|
||||
* values as specified by platform. This will be true
|
||||
* for GMACs connected to switch, and interfaces that
|
||||
* do not use a PHY.
|
||||
*/
|
||||
if (!(adapter->poll_required)) {
|
||||
if (adapter->forced_speed != SPEED_UNKNOWN) {
|
||||
/* set speed and duplex */
|
||||
cmd->base.speed = SPEED_1000;
|
||||
cmd->base.duplex = DUPLEX_FULL;
|
||||
|
||||
/* Populate capabilities advertised by self */
|
||||
linkmode_zero(cmd->link_modes.advertising);
|
||||
cmd->base.autoneg = 0;
|
||||
cmd->base.port = PORT_TP;
|
||||
cmd->base.transceiver = XCVR_EXTERNAL;
|
||||
} else {
|
||||
/* non link polled and non
|
||||
* forced speed/duplex interface
|
||||
*/
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_set_settings()
|
||||
* Set EDMA settings
|
||||
*/
|
||||
static int edma_set_settings(struct net_device *netdev,
|
||||
const struct ethtool_link_ksettings *cmd)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
struct phy_device *phydev = NULL;
|
||||
|
||||
if ((adapter->forced_speed != SPEED_UNKNOWN) &&
|
||||
!adapter->poll_required)
|
||||
return -EPERM;
|
||||
|
||||
phydev = adapter->phydev;
|
||||
linkmode_copy(phydev->advertising, cmd->link_modes.advertising);
|
||||
linkmode_copy(phydev->supported, cmd->link_modes.supported);
|
||||
phydev->autoneg = cmd->base.autoneg;
|
||||
phydev->speed = cmd->base.speed;
|
||||
phydev->duplex = cmd->base.duplex;
|
||||
|
||||
genphy_config_aneg(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_coalesce
|
||||
* get interrupt mitigation
|
||||
*/
|
||||
static int edma_get_coalesce(struct net_device *netdev,
|
||||
struct ethtool_coalesce *ec)
|
||||
{
|
||||
u32 reg_val;
|
||||
|
||||
edma_get_tx_rx_coalesce(®_val);
|
||||
|
||||
/* We read the Interrupt Moderation Timer(IMT) register value,
|
||||
* use lower 16 bit for rx and higher 16 bit for Tx. We do a
|
||||
* left shift by 1, because IMT resolution timer is 2usecs.
|
||||
* Hence the value given by the register is multiplied by 2 to
|
||||
* get the actual time in usecs.
|
||||
*/
|
||||
ec->tx_coalesce_usecs = (((reg_val >> 16) & 0xffff) << 1);
|
||||
ec->rx_coalesce_usecs = ((reg_val & 0xffff) << 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_set_coalesce
|
||||
* set interrupt mitigation
|
||||
*/
|
||||
static int edma_set_coalesce(struct net_device *netdev,
|
||||
struct ethtool_coalesce *ec)
|
||||
{
|
||||
if (ec->tx_coalesce_usecs)
|
||||
edma_change_tx_coalesce(ec->tx_coalesce_usecs);
|
||||
if (ec->rx_coalesce_usecs)
|
||||
edma_change_rx_coalesce(ec->rx_coalesce_usecs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_set_priv_flags()
|
||||
* Set EDMA private flags
|
||||
*/
|
||||
static int edma_set_priv_flags(struct net_device *netdev, u32 flags)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_priv_flags()
|
||||
* get edma driver flags
|
||||
*/
|
||||
static u32 edma_get_priv_flags(struct net_device *netdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_ringparam()
|
||||
* get ring size
|
||||
*/
|
||||
static void edma_get_ringparam(struct net_device *netdev,
|
||||
struct ethtool_ringparam *ring)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
|
||||
|
||||
ring->tx_max_pending = edma_cinfo->tx_ring_count;
|
||||
ring->rx_max_pending = edma_cinfo->rx_ring_count;
|
||||
}
|
||||
|
||||
/* Ethtool operations
|
||||
*/
|
||||
static const struct ethtool_ops edma_ethtool_ops = {
|
||||
.get_drvinfo = &edma_get_drvinfo,
|
||||
.get_link = ðtool_op_get_link,
|
||||
.get_msglevel = &edma_get_msglevel,
|
||||
.nway_reset = &edma_nway_reset,
|
||||
.get_wol = &edma_get_wol,
|
||||
.get_link_ksettings = &edma_get_settings,
|
||||
.set_link_ksettings = &edma_set_settings,
|
||||
.get_strings = &edma_get_strings,
|
||||
.get_sset_count = &edma_get_strset_count,
|
||||
.get_ethtool_stats = &edma_get_ethtool_stats,
|
||||
.get_coalesce = &edma_get_coalesce,
|
||||
.set_coalesce = &edma_set_coalesce,
|
||||
.get_priv_flags = edma_get_priv_flags,
|
||||
.set_priv_flags = edma_set_priv_flags,
|
||||
.get_ringparam = edma_get_ringparam,
|
||||
};
|
||||
|
||||
/* edma_set_ethtool_ops
|
||||
* Set ethtool operations
|
||||
*/
|
||||
void edma_set_ethtool_ops(struct net_device *netdev)
|
||||
{
|
||||
netdev->ethtool_ops = &edma_ethtool_ops;
|
||||
}
|
||||
@@ -0,0 +1,389 @@
|
||||
/*
|
||||
* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all copies.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _ESS_EDMA_H_
|
||||
#define _ESS_EDMA_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct edma_adapter;
|
||||
struct edma_hw;
|
||||
|
||||
/* register definition */
|
||||
#define EDMA_REG_MAS_CTRL 0x0
|
||||
#define EDMA_REG_TIMEOUT_CTRL 0x004
|
||||
#define EDMA_REG_DBG0 0x008
|
||||
#define EDMA_REG_DBG1 0x00C
|
||||
#define EDMA_REG_SW_CTRL0 0x100
|
||||
#define EDMA_REG_SW_CTRL1 0x104
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define EDMA_REG_RX_ISR 0x200
|
||||
#define EDMA_REG_TX_ISR 0x208
|
||||
#define EDMA_REG_MISC_ISR 0x210
|
||||
#define EDMA_REG_WOL_ISR 0x218
|
||||
|
||||
#define EDMA_MISC_ISR_RX_URG_Q(x) (1 << x)
|
||||
|
||||
#define EDMA_MISC_ISR_AXIR_TIMEOUT 0x00000100
|
||||
#define EDMA_MISC_ISR_AXIR_ERR 0x00000200
|
||||
#define EDMA_MISC_ISR_TXF_DEAD 0x00000400
|
||||
#define EDMA_MISC_ISR_AXIW_ERR 0x00000800
|
||||
#define EDMA_MISC_ISR_AXIW_TIMEOUT 0x00001000
|
||||
|
||||
#define EDMA_WOL_ISR 0x00000001
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
#define EDMA_REG_MISC_IMR 0x214
|
||||
#define EDMA_REG_WOL_IMR 0x218
|
||||
|
||||
#define EDMA_RX_IMR_NORMAL_MASK 0x1
|
||||
#define EDMA_TX_IMR_NORMAL_MASK 0x1
|
||||
#define EDMA_MISC_IMR_NORMAL_MASK 0x80001FFF
|
||||
#define EDMA_WOL_IMR_NORMAL_MASK 0x1
|
||||
|
||||
/* Edma receive consumer index */
|
||||
#define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
|
||||
/* Edma transmit consumer index */
|
||||
#define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
|
||||
|
||||
/* IRQ Moderator Initial Timer Register */
|
||||
#define EDMA_REG_IRQ_MODRT_TIMER_INIT 0x280
|
||||
#define EDMA_IRQ_MODRT_TIMER_MASK 0xFFFF
|
||||
#define EDMA_IRQ_MODRT_RX_TIMER_SHIFT 0
|
||||
#define EDMA_IRQ_MODRT_TX_TIMER_SHIFT 16
|
||||
|
||||
/* Interrupt Control Register */
|
||||
#define EDMA_REG_INTR_CTRL 0x284
|
||||
#define EDMA_INTR_CLR_TYP_SHIFT 0
|
||||
#define EDMA_INTR_SW_IDX_W_TYP_SHIFT 1
|
||||
#define EDMA_INTR_CLEAR_TYPE_W1 0
|
||||
#define EDMA_INTR_CLEAR_TYPE_R 1
|
||||
|
||||
/* RX Interrupt Mask Register */
|
||||
#define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* TX Interrupt mask register */
|
||||
#define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* Load Ptr Register
|
||||
* Software sets this bit after the initialization of the head and tail
|
||||
*/
|
||||
#define EDMA_REG_TX_SRAM_PART 0x400
|
||||
#define EDMA_LOAD_PTR_SHIFT 16
|
||||
|
||||
/* TXQ Control Register */
|
||||
#define EDMA_REG_TXQ_CTRL 0x404
|
||||
#define EDMA_TXQ_CTRL_IP_OPTION_EN 0x10
|
||||
#define EDMA_TXQ_CTRL_TXQ_EN 0x20
|
||||
#define EDMA_TXQ_CTRL_ENH_MODE 0x40
|
||||
#define EDMA_TXQ_CTRL_LS_8023_EN 0x80
|
||||
#define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100
|
||||
#define EDMA_TXQ_CTRL_LSO_BREAK_EN 0x200
|
||||
#define EDMA_TXQ_NUM_TPD_BURST_MASK 0xF
|
||||
#define EDMA_TXQ_TXF_BURST_NUM_MASK 0xFFFF
|
||||
#define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0
|
||||
#define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16
|
||||
|
||||
#define EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
|
||||
#define EDMA_TXF_WATER_MARK_MASK 0x0FFF
|
||||
#define EDMA_TXF_LOW_WATER_MARK_SHIFT 0
|
||||
#define EDMA_TXF_HIGH_WATER_MARK_SHIFT 16
|
||||
#define EDMA_TXQ_CTRL_BURST_MODE_EN 0x80000000
|
||||
|
||||
/* WRR Control Register */
|
||||
#define EDMA_REG_WRR_CTRL_Q0_Q3 0x40c
|
||||
#define EDMA_REG_WRR_CTRL_Q4_Q7 0x410
|
||||
#define EDMA_REG_WRR_CTRL_Q8_Q11 0x414
|
||||
#define EDMA_REG_WRR_CTRL_Q12_Q15 0x418
|
||||
|
||||
/* Weight round robin(WRR), it takes queue as input, and computes
|
||||
* starting bits where we need to write the weight for a particular
|
||||
* queue
|
||||
*/
|
||||
#define EDMA_WRR_SHIFT(x) (((x) * 5) % 20)
|
||||
|
||||
/* Tx Descriptor Control Register */
|
||||
#define EDMA_REG_TPD_RING_SIZE 0x41C
|
||||
#define EDMA_TPD_RING_SIZE_SHIFT 0
|
||||
#define EDMA_TPD_RING_SIZE_MASK 0xFFFF
|
||||
|
||||
/* Transmit descriptor base address */
|
||||
#define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* TPD Index Register */
|
||||
#define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
#define EDMA_TPD_PROD_IDX_BITS 0x0000FFFF
|
||||
#define EDMA_TPD_CONS_IDX_BITS 0xFFFF0000
|
||||
#define EDMA_TPD_PROD_IDX_MASK 0xFFFF
|
||||
#define EDMA_TPD_CONS_IDX_MASK 0xFFFF
|
||||
#define EDMA_TPD_PROD_IDX_SHIFT 0
|
||||
#define EDMA_TPD_CONS_IDX_SHIFT 16
|
||||
|
||||
/* TX Virtual Queue Mapping Control Register */
|
||||
#define EDMA_REG_VQ_CTRL0 0x4A0
|
||||
#define EDMA_REG_VQ_CTRL1 0x4A4
|
||||
|
||||
/* Virtual QID shift, it takes queue as input, and computes
|
||||
* Virtual QID position in virtual qid control register
|
||||
*/
|
||||
#define EDMA_VQ_ID_SHIFT(i) (((i) * 3) % 24)
|
||||
|
||||
/* Virtual Queue Default Value */
|
||||
#define EDMA_VQ_REG_VALUE 0x240240
|
||||
|
||||
/* Tx side Port Interface Control Register */
|
||||
#define EDMA_REG_PORT_CTRL 0x4A8
|
||||
#define EDMA_PAD_EN_SHIFT 15
|
||||
|
||||
/* Tx side VLAN Configuration Register */
|
||||
#define EDMA_REG_VLAN_CFG 0x4AC
|
||||
|
||||
#define EDMA_TX_CVLAN 16
|
||||
#define EDMA_TX_INS_CVLAN 17
|
||||
#define EDMA_TX_CVLAN_TAG_SHIFT 0
|
||||
|
||||
#define EDMA_TX_SVLAN 14
|
||||
#define EDMA_TX_INS_SVLAN 15
|
||||
#define EDMA_TX_SVLAN_TAG_SHIFT 16
|
||||
|
||||
/* Tx Queue Packet Statistic Register */
|
||||
#define EDMA_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
|
||||
|
||||
#define EDMA_TX_STAT_PKT_MASK 0xFFFFFF
|
||||
|
||||
/* Tx Queue Byte Statistic Register */
|
||||
#define EDMA_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
|
||||
|
||||
/* Load Balance Based Ring Offset Register */
|
||||
#define EDMA_REG_LB_RING 0x800
|
||||
#define EDMA_LB_RING_ENTRY_MASK 0xff
|
||||
#define EDMA_LB_RING_ID_MASK 0x7
|
||||
#define EDMA_LB_RING_PROFILE_ID_MASK 0x3
|
||||
#define EDMA_LB_RING_ENTRY_BIT_OFFSET 8
|
||||
#define EDMA_LB_RING_ID_OFFSET 0
|
||||
#define EDMA_LB_RING_PROFILE_ID_OFFSET 3
|
||||
#define EDMA_LB_REG_VALUE 0x6040200
|
||||
|
||||
/* Load Balance Priority Mapping Register */
|
||||
#define EDMA_REG_LB_PRI_START 0x804
|
||||
#define EDMA_REG_LB_PRI_END 0x810
|
||||
#define EDMA_LB_PRI_REG_INC 4
|
||||
#define EDMA_LB_PRI_ENTRY_BIT_OFFSET 4
|
||||
#define EDMA_LB_PRI_ENTRY_MASK 0xf
|
||||
|
||||
/* RSS Priority Mapping Register */
|
||||
#define EDMA_REG_RSS_PRI 0x820
|
||||
#define EDMA_RSS_PRI_ENTRY_MASK 0xf
|
||||
#define EDMA_RSS_RING_ID_MASK 0x7
|
||||
#define EDMA_RSS_PRI_ENTRY_BIT_OFFSET 4
|
||||
|
||||
/* RSS Indirection Register */
|
||||
#define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
|
||||
#define EDMA_NUM_IDT 16
|
||||
#define EDMA_RSS_IDT_VALUE 0x64206420
|
||||
|
||||
/* Default RSS Ring Register */
|
||||
#define EDMA_REG_DEF_RSS 0x890
|
||||
#define EDMA_DEF_RSS_MASK 0x7
|
||||
|
||||
/* RSS Hash Function Type Register */
|
||||
#define EDMA_REG_RSS_TYPE 0x894
|
||||
#define EDMA_RSS_TYPE_NONE 0x01
|
||||
#define EDMA_RSS_TYPE_IPV4TCP 0x02
|
||||
#define EDMA_RSS_TYPE_IPV6_TCP 0x04
|
||||
#define EDMA_RSS_TYPE_IPV4_UDP 0x08
|
||||
#define EDMA_RSS_TYPE_IPV6UDP 0x10
|
||||
#define EDMA_RSS_TYPE_IPV4 0x20
|
||||
#define EDMA_RSS_TYPE_IPV6 0x40
|
||||
#define EDMA_RSS_HASH_MODE_MASK 0x7f
|
||||
|
||||
#define EDMA_REG_RSS_HASH_VALUE 0x8C0
|
||||
|
||||
#define EDMA_REG_RSS_TYPE_RESULT 0x8C4
|
||||
|
||||
#define EDMA_HASH_TYPE_START 0
|
||||
#define EDMA_HASH_TYPE_END 5
|
||||
#define EDMA_HASH_TYPE_SHIFT 12
|
||||
|
||||
#define EDMA_RFS_FLOW_ENTRIES 1024
|
||||
#define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1)
|
||||
#define EDMA_RFS_EXPIRE_COUNT_PER_CALL 128
|
||||
|
||||
/* RFD Base Address Register */
|
||||
#define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* RFD Index Register */
|
||||
#define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2))
|
||||
|
||||
#define EDMA_RFD_PROD_IDX_BITS 0x00000FFF
|
||||
#define EDMA_RFD_CONS_IDX_BITS 0x0FFF0000
|
||||
#define EDMA_RFD_PROD_IDX_MASK 0xFFF
|
||||
#define EDMA_RFD_CONS_IDX_MASK 0xFFF
|
||||
#define EDMA_RFD_PROD_IDX_SHIFT 0
|
||||
#define EDMA_RFD_CONS_IDX_SHIFT 16
|
||||
|
||||
/* Rx Descriptor Control Register */
|
||||
#define EDMA_REG_RX_DESC0 0xA10
|
||||
#define EDMA_RFD_RING_SIZE_MASK 0xFFF
|
||||
#define EDMA_RX_BUF_SIZE_MASK 0xFFFF
|
||||
#define EDMA_RFD_RING_SIZE_SHIFT 0
|
||||
#define EDMA_RX_BUF_SIZE_SHIFT 16
|
||||
|
||||
#define EDMA_REG_RX_DESC1 0xA14
|
||||
#define EDMA_RXQ_RFD_BURST_NUM_MASK 0x3F
|
||||
#define EDMA_RXQ_RFD_PF_THRESH_MASK 0x1F
|
||||
#define EDMA_RXQ_RFD_LOW_THRESH_MASK 0xFFF
|
||||
#define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0
|
||||
#define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8
|
||||
#define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16
|
||||
|
||||
/* RXQ Control Register */
|
||||
#define EDMA_REG_RXQ_CTRL 0xA18
|
||||
#define EDMA_FIFO_THRESH_TYPE_SHIF 0
|
||||
#define EDMA_FIFO_THRESH_128_BYTE 0x0
|
||||
#define EDMA_FIFO_THRESH_64_BYTE 0x1
|
||||
#define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002
|
||||
#define EDMA_RXQ_CTRL_EN 0x0000FF00
|
||||
|
||||
/* AXI Burst Size Config */
|
||||
#define EDMA_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
|
||||
#define EDMA_AXIW_MAXWRSIZE_VALUE 0x0
|
||||
|
||||
/* Rx Statistics Register */
|
||||
#define EDMA_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
|
||||
#define EDMA_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* WoL Pattern Length Register */
|
||||
#define EDMA_REG_WOL_PATTERN_LEN0 0xC00
|
||||
#define EDMA_WOL_PT_LEN_MASK 0xFF
|
||||
#define EDMA_WOL_PT0_LEN_SHIFT 0
|
||||
#define EDMA_WOL_PT1_LEN_SHIFT 8
|
||||
#define EDMA_WOL_PT2_LEN_SHIFT 16
|
||||
#define EDMA_WOL_PT3_LEN_SHIFT 24
|
||||
|
||||
#define EDMA_REG_WOL_PATTERN_LEN1 0xC04
|
||||
#define EDMA_WOL_PT4_LEN_SHIFT 0
|
||||
#define EDMA_WOL_PT5_LEN_SHIFT 8
|
||||
#define EDMA_WOL_PT6_LEN_SHIFT 16
|
||||
|
||||
/* WoL Control Register */
|
||||
#define EDMA_REG_WOL_CTRL 0xC08
|
||||
#define EDMA_WOL_WK_EN 0x00000001
|
||||
#define EDMA_WOL_MG_EN 0x00000002
|
||||
#define EDMA_WOL_PT0_EN 0x00000004
|
||||
#define EDMA_WOL_PT1_EN 0x00000008
|
||||
#define EDMA_WOL_PT2_EN 0x00000010
|
||||
#define EDMA_WOL_PT3_EN 0x00000020
|
||||
#define EDMA_WOL_PT4_EN 0x00000040
|
||||
#define EDMA_WOL_PT5_EN 0x00000080
|
||||
#define EDMA_WOL_PT6_EN 0x00000100
|
||||
|
||||
/* MAC Control Register */
|
||||
#define EDMA_REG_MAC_CTRL0 0xC20
|
||||
#define EDMA_REG_MAC_CTRL1 0xC24
|
||||
|
||||
/* WoL Pattern Register */
|
||||
#define EDMA_REG_WOL_PATTERN_START 0x5000
|
||||
#define EDMA_PATTERN_PART_REG_OFFSET 0x40
|
||||
|
||||
|
||||
/* TX descriptor fields */
|
||||
#define EDMA_TPD_HDR_SHIFT 0
|
||||
#define EDMA_TPD_PPPOE_EN 0x00000100
|
||||
#define EDMA_TPD_IP_CSUM_EN 0x00000200
|
||||
#define EDMA_TPD_TCP_CSUM_EN 0x0000400
|
||||
#define EDMA_TPD_UDP_CSUM_EN 0x00000800
|
||||
#define EDMA_TPD_CUSTOM_CSUM_EN 0x00000C00
|
||||
#define EDMA_TPD_LSO_EN 0x00001000
|
||||
#define EDMA_TPD_LSO_V2_EN 0x00002000
|
||||
#define EDMA_TPD_IPV4_EN 0x00010000
|
||||
#define EDMA_TPD_MSS_MASK 0x1FFF
|
||||
#define EDMA_TPD_MSS_SHIFT 18
|
||||
#define EDMA_TPD_CUSTOM_CSUM_SHIFT 18
|
||||
|
||||
/* RRD descriptor fields */
|
||||
#define EDMA_RRD_NUM_RFD_MASK 0x000F
|
||||
#define EDMA_RRD_SVLAN 0x8000
|
||||
#define EDMA_RRD_FLOW_COOKIE_MASK 0x07FF;
|
||||
|
||||
#define EDMA_RRD_PKT_SIZE_MASK 0x3FFF
|
||||
#define EDMA_RRD_CSUM_FAIL_MASK 0xC000
|
||||
#define EDMA_RRD_CVLAN 0x0001
|
||||
#define EDMA_RRD_DESC_VALID 0x8000
|
||||
|
||||
#define EDMA_RRD_PRIORITY_SHIFT 4
|
||||
#define EDMA_RRD_PRIORITY_MASK 0x7
|
||||
#define EDMA_RRD_PORT_TYPE_SHIFT 7
|
||||
#define EDMA_RRD_PORT_TYPE_MASK 0x1F
|
||||
|
||||
#define ESS_RGMII_CTRL 0x0004
|
||||
|
||||
/* Port status registers */
|
||||
#define ESS_PORT0_STATUS 0x007C
|
||||
#define ESS_PORT1_STATUS 0x0080
|
||||
#define ESS_PORT2_STATUS 0x0084
|
||||
#define ESS_PORT3_STATUS 0x0088
|
||||
#define ESS_PORT4_STATUS 0x008C
|
||||
#define ESS_PORT5_STATUS 0x0090
|
||||
|
||||
#define ESS_PORT_STATUS_HDX_FLOW_CTL 0x80
|
||||
#define ESS_PORT_STATUS_DUPLEX_MODE 0x40
|
||||
#define ESS_PORT_STATUS_RX_FLOW_EN 0x20
|
||||
#define ESS_PORT_STATUS_TX_FLOW_EN 0x10
|
||||
#define ESS_PORT_STATUS_RX_MAC_EN 0x08
|
||||
#define ESS_PORT_STATUS_TX_MAC_EN 0x04
|
||||
#define ESS_PORT_STATUS_SPEED_INV 0x03
|
||||
#define ESS_PORT_STATUS_SPEED_1000 0x02
|
||||
#define ESS_PORT_STATUS_SPEED_100 0x01
|
||||
#define ESS_PORT_STATUS_SPEED_10 0x00
|
||||
|
||||
#define ESS_PORT_1G_FDX (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \
|
||||
ESS_PORT_STATUS_TX_FLOW_EN | ESS_PORT_STATUS_RX_MAC_EN | \
|
||||
ESS_PORT_STATUS_TX_MAC_EN | ESS_PORT_STATUS_SPEED_1000)
|
||||
|
||||
#define PHY_STATUS_REG 0x11
|
||||
#define PHY_STATUS_SPEED 0xC000
|
||||
#define PHY_STATUS_SPEED_SHIFT 14
|
||||
#define PHY_STATUS_DUPLEX 0x2000
|
||||
#define PHY_STATUS_DUPLEX_SHIFT 13
|
||||
#define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800
|
||||
#define PHY_STATUS_CARRIER 0x0400
|
||||
#define PHY_STATUS_CARRIER_SHIFT 10
|
||||
|
||||
/* Port lookup control registers */
|
||||
#define ESS_PORT0_LOOKUP_CTRL 0x0660
|
||||
#define ESS_PORT1_LOOKUP_CTRL 0x066C
|
||||
#define ESS_PORT2_LOOKUP_CTRL 0x0678
|
||||
#define ESS_PORT3_LOOKUP_CTRL 0x0684
|
||||
#define ESS_PORT4_LOOKUP_CTRL 0x0690
|
||||
#define ESS_PORT5_LOOKUP_CTRL 0x069C
|
||||
|
||||
#define ESS_PORT0_HEADER_CTRL 0x009C
|
||||
|
||||
#define ESS_PORTS_ALL 0x3f
|
||||
|
||||
#define ESS_FWD_CTRL1 0x0624
|
||||
#define ESS_FWD_CTRL1_UC_FLOOD BITS(0, 7)
|
||||
#define ESS_FWD_CTRL1_UC_FLOOD_S 0
|
||||
#define ESS_FWD_CTRL1_MC_FLOOD BITS(8, 7)
|
||||
#define ESS_FWD_CTRL1_MC_FLOOD_S 8
|
||||
#define ESS_FWD_CTRL1_BC_FLOOD BITS(16, 7)
|
||||
#define ESS_FWD_CTRL1_BC_FLOOD_S 16
|
||||
#define ESS_FWD_CTRL1_IGMP BITS(24, 7)
|
||||
#define ESS_FWD_CTRL1_IGMP_S 24
|
||||
|
||||
#endif /* _ESS_EDMA_H_ */
|
||||
2118
target/linux/ipq40xx/files/drivers/net/phy/ar40xx.c
Normal file
2118
target/linux/ipq40xx/files/drivers/net/phy/ar40xx.c
Normal file
File diff suppressed because it is too large
Load Diff
342
target/linux/ipq40xx/files/drivers/net/phy/ar40xx.h
Normal file
342
target/linux/ipq40xx/files/drivers/net/phy/ar40xx.h
Normal file
@@ -0,0 +1,342 @@
|
||||
/*
|
||||
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all copies.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __AR40XX_H
|
||||
#define __AR40XX_H
|
||||
|
||||
#define AR40XX_MAX_VLANS 128
|
||||
#define AR40XX_NUM_PORTS 6
|
||||
#define AR40XX_NUM_PHYS 5
|
||||
|
||||
#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
|
||||
|
||||
struct ar40xx_priv {
|
||||
struct switch_dev dev;
|
||||
|
||||
u8 __iomem *hw_addr;
|
||||
u8 __iomem *psgmii_hw_addr;
|
||||
u32 mac_mode;
|
||||
struct reset_control *ess_rst;
|
||||
u32 cpu_bmp;
|
||||
u32 lan_bmp;
|
||||
u32 wan_bmp;
|
||||
|
||||
struct mii_bus *mii_bus;
|
||||
struct phy_device *phy;
|
||||
|
||||
/* mutex for qm task */
|
||||
struct mutex qm_lock;
|
||||
struct delayed_work qm_dwork;
|
||||
u32 port_link_up[AR40XX_NUM_PORTS];
|
||||
u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
|
||||
u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
|
||||
|
||||
u32 phy_t_status;
|
||||
|
||||
/* mutex for switch reg access */
|
||||
struct mutex reg_mutex;
|
||||
|
||||
/* mutex for mib task */
|
||||
struct mutex mib_lock;
|
||||
struct delayed_work mib_work;
|
||||
int mib_next_port;
|
||||
u64 *mib_stats;
|
||||
|
||||
char buf[2048];
|
||||
|
||||
/* all fields below will be cleared on reset */
|
||||
bool vlan;
|
||||
u16 vlan_id[AR40XX_MAX_VLANS];
|
||||
u8 vlan_table[AR40XX_MAX_VLANS];
|
||||
u8 vlan_tagged;
|
||||
u16 pvid[AR40XX_NUM_PORTS];
|
||||
|
||||
/* mirror */
|
||||
bool mirror_rx;
|
||||
bool mirror_tx;
|
||||
int source_port;
|
||||
int monitor_port;
|
||||
};
|
||||
|
||||
#define AR40XX_PORT_LINK_UP 1
|
||||
#define AR40XX_PORT_LINK_DOWN 0
|
||||
#define AR40XX_QM_NOT_EMPTY 1
|
||||
#define AR40XX_QM_EMPTY 0
|
||||
|
||||
#define AR40XX_LAN_VLAN 1
|
||||
#define AR40XX_WAN_VLAN 2
|
||||
|
||||
enum ar40xx_port_wrapper_cfg {
|
||||
PORT_WRAPPER_PSGMII = 0,
|
||||
};
|
||||
|
||||
struct ar40xx_mib_desc {
|
||||
u32 size;
|
||||
u32 offset;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
#define AR40XX_PORT_CPU 0
|
||||
|
||||
#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
|
||||
#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
|
||||
|
||||
#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
|
||||
|
||||
#define AR40XX_MII_ATH_MMD_ADDR 0x0d
|
||||
#define AR40XX_MII_ATH_MMD_DATA 0x0e
|
||||
#define AR40XX_MII_ATH_DBG_ADDR 0x1d
|
||||
#define AR40XX_MII_ATH_DBG_DATA 0x1e
|
||||
|
||||
#define AR40XX_STATS_RXBROAD 0x00
|
||||
#define AR40XX_STATS_RXPAUSE 0x04
|
||||
#define AR40XX_STATS_RXMULTI 0x08
|
||||
#define AR40XX_STATS_RXFCSERR 0x0c
|
||||
#define AR40XX_STATS_RXALIGNERR 0x10
|
||||
#define AR40XX_STATS_RXRUNT 0x14
|
||||
#define AR40XX_STATS_RXFRAGMENT 0x18
|
||||
#define AR40XX_STATS_RX64BYTE 0x1c
|
||||
#define AR40XX_STATS_RX128BYTE 0x20
|
||||
#define AR40XX_STATS_RX256BYTE 0x24
|
||||
#define AR40XX_STATS_RX512BYTE 0x28
|
||||
#define AR40XX_STATS_RX1024BYTE 0x2c
|
||||
#define AR40XX_STATS_RX1518BYTE 0x30
|
||||
#define AR40XX_STATS_RXMAXBYTE 0x34
|
||||
#define AR40XX_STATS_RXTOOLONG 0x38
|
||||
#define AR40XX_STATS_RXGOODBYTE 0x3c
|
||||
#define AR40XX_STATS_RXBADBYTE 0x44
|
||||
#define AR40XX_STATS_RXOVERFLOW 0x4c
|
||||
#define AR40XX_STATS_FILTERED 0x50
|
||||
#define AR40XX_STATS_TXBROAD 0x54
|
||||
#define AR40XX_STATS_TXPAUSE 0x58
|
||||
#define AR40XX_STATS_TXMULTI 0x5c
|
||||
#define AR40XX_STATS_TXUNDERRUN 0x60
|
||||
#define AR40XX_STATS_TX64BYTE 0x64
|
||||
#define AR40XX_STATS_TX128BYTE 0x68
|
||||
#define AR40XX_STATS_TX256BYTE 0x6c
|
||||
#define AR40XX_STATS_TX512BYTE 0x70
|
||||
#define AR40XX_STATS_TX1024BYTE 0x74
|
||||
#define AR40XX_STATS_TX1518BYTE 0x78
|
||||
#define AR40XX_STATS_TXMAXBYTE 0x7c
|
||||
#define AR40XX_STATS_TXOVERSIZE 0x80
|
||||
#define AR40XX_STATS_TXBYTE 0x84
|
||||
#define AR40XX_STATS_TXCOLLISION 0x8c
|
||||
#define AR40XX_STATS_TXABORTCOL 0x90
|
||||
#define AR40XX_STATS_TXMULTICOL 0x94
|
||||
#define AR40XX_STATS_TXSINGLECOL 0x98
|
||||
#define AR40XX_STATS_TXEXCDEFER 0x9c
|
||||
#define AR40XX_STATS_TXDEFER 0xa0
|
||||
#define AR40XX_STATS_TXLATECOL 0xa4
|
||||
|
||||
#define AR40XX_REG_MODULE_EN 0x030
|
||||
#define AR40XX_MODULE_EN_MIB BIT(0)
|
||||
|
||||
#define AR40XX_REG_MIB_FUNC 0x034
|
||||
#define AR40XX_MIB_BUSY BIT(17)
|
||||
#define AR40XX_MIB_CPU_KEEP BIT(20)
|
||||
#define AR40XX_MIB_FUNC BITS(24, 3)
|
||||
#define AR40XX_MIB_FUNC_S 24
|
||||
#define AR40XX_MIB_FUNC_NO_OP 0x0
|
||||
#define AR40XX_MIB_FUNC_FLUSH 0x1
|
||||
|
||||
#define AR40XX_ESS_SERVICE_TAG 0x48
|
||||
#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
|
||||
|
||||
#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
|
||||
#define AR40XX_PORT_SPEED BITS(0, 2)
|
||||
#define AR40XX_PORT_STATUS_SPEED_S 0
|
||||
#define AR40XX_PORT_TX_EN BIT(2)
|
||||
#define AR40XX_PORT_RX_EN BIT(3)
|
||||
#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
|
||||
#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
|
||||
#define AR40XX_PORT_DUPLEX BIT(6)
|
||||
#define AR40XX_PORT_TXHALF_FLOW BIT(7)
|
||||
#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
|
||||
#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
|
||||
#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
|
||||
|
||||
#define AR40XX_REG_MAX_FRAME_SIZE 0x078
|
||||
#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
|
||||
|
||||
#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
|
||||
|
||||
#define AR40XX_REG_EEE_CTRL 0x100
|
||||
#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
|
||||
|
||||
#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
|
||||
#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
|
||||
#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
|
||||
#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
|
||||
#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
|
||||
|
||||
#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
|
||||
#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
|
||||
#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
|
||||
#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
|
||||
#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
|
||||
#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
|
||||
#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
|
||||
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
|
||||
#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
|
||||
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
|
||||
|
||||
#define AR40XX_REG_VTU_FUNC0 0x0610
|
||||
#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
|
||||
#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
|
||||
#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
|
||||
#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
|
||||
#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
|
||||
#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
|
||||
#define AR40XX_VTU_FUNC0_IVL BIT(19)
|
||||
#define AR40XX_VTU_FUNC0_VALID BIT(20)
|
||||
|
||||
#define AR40XX_REG_VTU_FUNC1 0x0614
|
||||
#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
|
||||
#define AR40XX_VTU_FUNC1_OP_NOOP 0
|
||||
#define AR40XX_VTU_FUNC1_OP_FLUSH 1
|
||||
#define AR40XX_VTU_FUNC1_OP_LOAD 2
|
||||
#define AR40XX_VTU_FUNC1_OP_PURGE 3
|
||||
#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
|
||||
#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
|
||||
#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
|
||||
#define AR40XX_VTU_FUNC1_FULL BIT(4)
|
||||
#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
|
||||
#define AR40XX_VTU_FUNC1_PORT_S 8
|
||||
#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
|
||||
#define AR40XX_VTU_FUNC1_VID_S 16
|
||||
#define AR40XX_VTU_FUNC1_BUSY BIT(31)
|
||||
|
||||
#define AR40XX_REG_FWD_CTRL0 0x620
|
||||
#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
|
||||
#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
|
||||
#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
|
||||
|
||||
#define AR40XX_REG_FWD_CTRL1 0x624
|
||||
#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
|
||||
#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
|
||||
#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
|
||||
#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
|
||||
#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
|
||||
#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
|
||||
#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
|
||||
#define AR40XX_FWD_CTRL1_IGMP_S 24
|
||||
|
||||
#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
|
||||
#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
|
||||
#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
|
||||
#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
|
||||
#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
|
||||
#define AR40XX_PORT_LOOKUP_STATE_S 16
|
||||
#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
|
||||
#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
|
||||
#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
|
||||
|
||||
#define AR40XX_REG_ATU_FUNC 0x60c
|
||||
#define AR40XX_ATU_FUNC_OP BITS(0, 4)
|
||||
#define AR40XX_ATU_FUNC_OP_NOOP 0x0
|
||||
#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
|
||||
#define AR40XX_ATU_FUNC_OP_LOAD 0x2
|
||||
#define AR40XX_ATU_FUNC_OP_PURGE 0x3
|
||||
#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
|
||||
#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
|
||||
#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
|
||||
#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
|
||||
#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
|
||||
#define AR40XX_ATU_FUNC_BUSY BIT(31)
|
||||
|
||||
#define AR40XX_REG_QM_DEBUG_ADDR 0x820
|
||||
#define AR40XX_REG_QM_DEBUG_VALUE 0x824
|
||||
#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
|
||||
#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
|
||||
|
||||
#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
|
||||
#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
|
||||
|
||||
#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
|
||||
#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
|
||||
#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
|
||||
|
||||
#define AR40XX_PHY_DEBUG_0 0
|
||||
#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
|
||||
|
||||
#define AR40XX_PHY_DEBUG_2 2
|
||||
|
||||
#define AR40XX_PHY_SPEC_STATUS 0x11
|
||||
#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
|
||||
#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
|
||||
#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
|
||||
|
||||
/* port forwarding state */
|
||||
enum {
|
||||
AR40XX_PORT_STATE_DISABLED = 0,
|
||||
AR40XX_PORT_STATE_BLOCK = 1,
|
||||
AR40XX_PORT_STATE_LISTEN = 2,
|
||||
AR40XX_PORT_STATE_LEARN = 3,
|
||||
AR40XX_PORT_STATE_FORWARD = 4
|
||||
};
|
||||
|
||||
/* ingress 802.1q mode */
|
||||
enum {
|
||||
AR40XX_IN_PORT_ONLY = 0,
|
||||
AR40XX_IN_PORT_FALLBACK = 1,
|
||||
AR40XX_IN_VLAN_ONLY = 2,
|
||||
AR40XX_IN_SECURE = 3
|
||||
};
|
||||
|
||||
/* egress 802.1q mode */
|
||||
enum {
|
||||
AR40XX_OUT_KEEP = 0,
|
||||
AR40XX_OUT_STRIP_VLAN = 1,
|
||||
AR40XX_OUT_ADD_VLAN = 2
|
||||
};
|
||||
|
||||
/* port speed */
|
||||
enum {
|
||||
AR40XX_PORT_SPEED_10M = 0,
|
||||
AR40XX_PORT_SPEED_100M = 1,
|
||||
AR40XX_PORT_SPEED_1000M = 2,
|
||||
AR40XX_PORT_SPEED_ERR = 3,
|
||||
};
|
||||
|
||||
#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
|
||||
|
||||
#define AR40XX_QM_WORK_DELAY 100
|
||||
|
||||
#define AR40XX_MIB_FUNC_CAPTURE 0x3
|
||||
|
||||
#define AR40XX_REG_PORT_STATS_START 0x1000
|
||||
#define AR40XX_REG_PORT_STATS_LEN 0x100
|
||||
|
||||
#define AR40XX_PORTS_ALL 0x3f
|
||||
|
||||
#define AR40XX_PSGMII_ID 5
|
||||
#define AR40XX_PSGMII_CALB_NUM 100
|
||||
#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
|
||||
#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
|
||||
#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
|
||||
#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
|
||||
#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
|
||||
#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
|
||||
#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
|
||||
#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
|
||||
#define AR40XX_MALIBU_PHY_LAST_ADDR 4
|
||||
|
||||
static inline struct ar40xx_priv *
|
||||
swdev_to_ar40xx(struct switch_dev *swdev)
|
||||
{
|
||||
return container_of(swdev, struct ar40xx_priv, dev);
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user