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ralink: add xhci driver

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Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 39328
This commit is contained in:
John Crispin
2014-01-19 17:27:13 +00:00
parent 2f5f498969
commit a75b692557
12 changed files with 5715 additions and 0 deletions
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445
target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.c Normal file
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#include "mtk-phy.h"
#ifdef CONFIG_PROJECT_7621
#include "mtk-phy-7621.h"
//not used on SoC
PHY_INT32 phy_init(struct u3phy_info *info){
return PHY_TRUE;
}
//not used on SoC
PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
return PHY_TRUE;
}
//--------------------------------------------------------
// Function : fgEyeScanHelper_CheckPtInRegion()
// Description : Check if the test point is in a rectangle region.
// If it is in the rectangle, also check if this point
// is on the multiple of deltaX and deltaY.
// Parameter : strucScanRegion * prEye - the region
// BYTE bX
// BYTE bY
// Return : BYTE - TRUE : This point needs to be tested
// FALSE: This point will be omitted
// Note : First check within the rectangle.
// Secondly, use modulous to check if the point will be tested.
//--------------------------------------------------------
static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
{
PHY_INT8 fgValid = true;
/// Be careful, the axis origin is on the TOP-LEFT corner.
/// Therefore the top-left point has the minimum X and Y
/// Botton-right point is the maximum X and Y
if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
&& (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
{
// With the region, now check whether or not the input test point is
// on the multiples of X and Y
// Do not have to worry about negative value, because we have already
// check the input bX, and bY is within the region.
if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
|| ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
{
// if the division will have remainder, that means
// the input test point is on the multiples of X and Y
fgValid = false;
}
else
{
}
}
else
{
fgValid = false;
}
return fgValid;
}
//--------------------------------------------------------
// Function : EyeScanHelper_RunTest()
// Description : Enable the test, and wait til it is completed
// Parameter : None
// Return : None
// Note : None
//--------------------------------------------------------
static void EyeScanHelper_RunTest(struct u3phy_info *info)
{
DRV_UDELAY(100);
// Disable the test
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
DRV_UDELAY(100);
// Run the test
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
DRV_UDELAY(100);
// Wait til it's done
//RGS_SSUSB_RX_EYE_CNT_RDY
while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
, RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
}
//--------------------------------------------------------
// Function : fgEyeScanHelper_CalNextPoint()
// Description : Calcualte the test point for the measurement
// Parameter : None
// Return : BOOL - TRUE : the next point is within the
// boundaryof HW limit
// FALSE: the next point is out of the HW limit
// Note : The next point is obtained by calculating
// from the bottom left of the region rectangle
// and then scanning up until it reaches the upper
// limit. At this time, the x will increment, and
// start scanning downwards until the y hits the
// zero.
//--------------------------------------------------------
static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
{
if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
|| ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
)
{
/// Reaches the limit of Y axis
/// Increment X
_bXcurr++;
_fgXChged = true;
_eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
if (_bXcurr > MAX_X)
{
return false;
}
}
else
{
_bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
_fgXChged = false;
}
return PHY_TRUE;
}
PHY_INT32 eyescan_init(struct u3phy_info *info){
//initial PHY setting
U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
, RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
, RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
return PHY_TRUE;
}
PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
PHY_INT32 cOfst = 0;
PHY_UINT8 bIdxX = 0;
PHY_UINT8 bIdxY = 0;
//PHY_INT8 bCnt = 0;
PHY_UINT8 bIdxCycCnt = 0;
PHY_INT8 fgValid;
PHY_INT8 cX;
PHY_INT8 cY;
PHY_UINT8 bExtendCnt;
PHY_INT8 isContinue;
//PHY_INT8 isBreak;
PHY_UINT32 wErr0 = 0, wErr1 = 0;
//PHY_UINT32 temp;
PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
_rEye1.bX_tl = x_t1;
_rEye1.bY_tl = y_t1;
_rEye1.bX_br = x_br;
_rEye1.bY_br = y_br;
_rEye1.bDeltaX = delta_x;
_rEye1.bDeltaY = delta_y;
_rEye2.bX_tl = x_t1;
_rEye2.bY_tl = y_t1;
_rEye2.bX_br = x_br;
_rEye2.bY_br = y_br;
_rEye2.bDeltaX = delta_x;
_rEye2.bDeltaY = delta_y;
_rTestCycle.wEyeCnt = eye_cnt;
_rTestCycle.bNumOfEyeCnt = num_cnt;
_rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
_rTestCycle.bPICalEn = PI_cal_en;
_bXcurr = 0;
_bYcurr = 0;
_eScanDir = SCAN_DN;
_fgXChged = false;
printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
//force SIGDET to OFF
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
, RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
// RX_TRI_DET_EN to Disable
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
, RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
if (PI_cal_en){
// PI Calibration
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
DRV_UDELAY(20);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
_bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
, RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
printk(KERN_ERR "PI result: %d\n", _bPIResult);
}
// Read Initial DAC
// Set CYCLE
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
// Eye Monitor Feature
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
, RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
// Move X,Y to the top-left corner
for (cOfst = 0; cOfst >= -64; cOfst--)
{
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
}
for (cOfst = 0; cOfst < 64; cOfst++)
{
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
}
//ClearErrorResult
for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
{
for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
}
}
}
isContinue = true;
while(isContinue){
//printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
// The point is within the boundary, then let's check if it is within
// the testing region.
// The point is only test-able if one of the eye region
// includes this point.
fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
|| fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
// Translate bX and bY to 2's complement from where the origin was on the
// top left corner.
// 0x40 and 0x3F needs a bit of thinking!!!! >"<
cX = (_bXcurr ^ 0x40);
cY = (_bYcurr ^ 0x3F);
// Set X if necessary
if (_fgXChged == true)
{
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
}
// Set Y
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
/// Test this point!
if (fgValid){
for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
{
//run test
EyeScanHelper_RunTest(info);
}
for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
{
EyeScanHelper_RunTest(info);
wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
//EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
}
//printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
}
else{
}
if (fgEyeScanHelper_CalNextPoint() == false){
#if 0
printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
#endif
printk(KERN_ERR "end of eye scan\n");
isContinue = false;
}
}
printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
, U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
, U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
// Move X,Y to the top-left corner
for (cOfst = 63; cOfst >= 0; cOfst--)
{
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
}
for (cOfst = 63; cOfst >= 0; cOfst--)
{
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
}
printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
, U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
, U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
printk(KERN_ERR "PI result: %d\n", _bPIResult);
printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
return PHY_TRUE;
}
//not used on SoC
PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
return PHY_TRUE;
}
//not used on SoC
PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
return PHY_TRUE;
}
PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
PHY_INT32 i=0;
//PHY_INT32 j=0;
//PHY_INT8 u1SrCalVal = 0;
//PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
PHY_INT32 fgRet = 0;
PHY_INT32 u4FmOut = 0;
PHY_INT32 u4Tmp = 0;
//PHY_INT32 temp;
// => RG_USB20_HSTX_SRCAL_EN = 1
// enable HS TX SR calibration
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
, RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
DRV_MSLEEP(1);
// => RG_FRCK_EN = 1
// Enable free run clock
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
, RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
// MT6290 HS signal quality patch
// => RG_CYCLECNT = 400
// Setting cyclecnt =400
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
, RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
// => RG_FREQDET_EN = 1
// Enable frequency meter
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
, RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
// wait for FM detection done, set 10ms timeout
for(i=0; i<10; i++){
// => u4FmOut = USB_FM_OUT
// read FM_OUT
u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
// check if FM detection done
if (u4FmOut != 0)
{
fgRet = 0;
printk("FM detection done! loop = %d\n", i);
break;
}
fgRet = 1;
DRV_MSLEEP(1);
}
// => RG_FREQDET_EN = 0
// disable frequency meter
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
, RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
// => RG_FRCK_EN = 0
// disable free run clock
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
, RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
// => RG_USB20_HSTX_SRCAL_EN = 0
// disable HS TX SR calibration
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
, RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
DRV_MSLEEP(1);
if(u4FmOut == 0){
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
, RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
fgRet = 1;
}
else{
// set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
, RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
}
return fgRet;
}
#endif

2871
target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.h Normal file
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58
target/linux/ramips/files/drivers/usb/host/mtk-phy-ahb.c Normal file
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@@ -0,0 +1,58 @@
#include "mtk-phy.h"
#ifdef CONFIG_U3D_HAL_SUPPORT
#include "mu3d_hal_osal.h"
#endif
#ifdef CONFIG_U3_PHY_AHB_SUPPORT
#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#ifndef CONFIG_U3D_HAL_SUPPORT
#define os_writel(addr,data) {\
(*((volatile PHY_UINT32*)(addr)) = data);\
}
#define os_readl(addr) *((volatile PHY_UINT32*)(addr))
#define os_writelmsk(addr, data, msk) \
{ os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
}
#define os_setmsk(addr, msk) \
{ os_writel(addr, os_readl(addr) | msk); \
}
#define os_clrmsk(addr, msk) \
{ os_writel(addr, os_readl(addr) &~ msk); \
}
/*msk the data first, then umsk with the umsk.*/
#define os_writelmskumsk(addr, data, msk, umsk) \
{\
os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
}
#endif
PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
{
os_writel(addr, data);
return 0;
}
PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
{
return os_readl(addr);
}
PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
{
os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
return 0;
}
PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
{
return ((os_readl(addr)>>((addr%4)*8))&0xff);
}
#endif

102
target/linux/ramips/files/drivers/usb/host/mtk-phy.c Normal file
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#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#define U3_PHY_LIB
#include "mtk-phy.h"
#ifdef CONFIG_PROJECT_7621
#include "mtk-phy-7621.h"
#endif
#ifdef CONFIG_PROJECT_PHY
static struct u3phy_operator project_operators = {
.init = phy_init,
.change_pipe_phase = phy_change_pipe_phase,
.eyescan_init = eyescan_init,
.eyescan = phy_eyescan,
.u2_slew_rate_calibration = u2_slew_rate_calibration,
};
#endif
PHY_INT32 u3phy_init(){
#ifndef CONFIG_PROJECT_PHY
PHY_INT32 u3phy_version;
#endif
if(u3phy != NULL){
return PHY_TRUE;
}
u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
#endif
#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
u3phy->phyd_version_addr = 0x2000e4;
#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
u3phy_p1->phyd_version_addr = 0x2000e4;
#endif
#else
u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
#endif
#endif
#ifdef CONFIG_PROJECT_PHY
u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
u3phy_ops = &project_operators;
#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
#endif
#endif
return PHY_TRUE;
}
PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
PHY_INT8 cur_value;
PHY_INT8 new_value;
cur_value = U3PhyReadReg8(addr);
new_value = (cur_value & (~mask)) | (value << offset);
//udelay(i2cdelayus);
U3PhyWriteReg8(addr, new_value);
return PHY_TRUE;
}
PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
PHY_INT32 cur_value;
PHY_INT32 new_value;
cur_value = U3PhyReadReg32(addr);
new_value = (cur_value & (~mask)) | ((value << offset) & mask);
U3PhyWriteReg32(addr, new_value);
//DRV_MDELAY(100);
return PHY_TRUE;
}
PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
return ((U3PhyReadReg8(addr) & mask) >> offset);
}
PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
return ((U3PhyReadReg32(addr) & mask) >> offset);
}

179
target/linux/ramips/files/drivers/usb/host/mtk-phy.h Normal file
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#ifndef __MTK_PHY_NEW_H
#define __MTK_PHY_NEW_H
//#define CONFIG_U3D_HAL_SUPPORT
/* include system library */
#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/delay.h>
/* Choose PHY R/W implementation */
//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
/* Choose PHY version */
//Select your project by defining one of the followings
#define CONFIG_PROJECT_7621 //7621
#define CONFIG_PROJECT_PHY
/* BASE ADDRESS DEFINE, should define this on ASIC */
#define PHY_BASE 0xBE1D0000
#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
#define U2_PHY_BASE (PHY_BASE+0x800)
#define U3_PHYD_BASE (PHY_BASE+0x900)
#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
#define U3_PHYA_BASE (PHY_BASE+0xb00)
#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
#endif
/*
0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
*/
/* TYPE DEFINE */
typedef unsigned int PHY_UINT32;
typedef int PHY_INT32;
typedef unsigned short PHY_UINT16;
typedef short PHY_INT16;
typedef unsigned char PHY_UINT8;
typedef char PHY_INT8;
typedef PHY_UINT32 __bitwise PHY_LE32;
/* CONSTANT DEFINE */
#define PHY_FALSE 0
#define PHY_TRUE 1
/* MACRO DEFINE */
#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
#define DRV_MDELAY mdelay
#define DRV_MSLEEP msleep
#define DRV_UDELAY udelay
#define DRV_USLEEP usleep
/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
struct u3phy_info {
PHY_INT32 phy_version;
PHY_INT32 phyd_version_addr;
#ifdef CONFIG_PROJECT_PHY
struct u2phy_reg *u2phy_regs;
struct u3phya_reg *u3phya_regs;
struct u3phya_da_reg *u3phya_da_regs;
struct u3phyd_reg *u3phyd_regs;
struct u3phyd_bank2_reg *u3phyd_bank2_regs;
struct sifslv_chip_reg *sifslv_chip_regs;
struct sifslv_fm_feg *sifslv_fm_regs;
#endif
};
struct u3phy_operator {
PHY_INT32 (*init) (struct u3phy_info *info);
PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
};
#ifdef U3_PHY_LIB
#define AUTOEXT
#else
#define AUTOEXT extern
#endif
AUTOEXT struct u3phy_info *u3phy;
AUTOEXT struct u3phy_info *u3phy_p1;
AUTOEXT struct u3phy_operator *u3phy_ops;
/*********eye scan required*********/
#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
typedef enum
{
SCAN_UP,
SCAN_DN
} enumScanDir;
struct strucScanRegion
{
PHY_INT8 bX_tl;
PHY_INT8 bY_tl;
PHY_INT8 bX_br;
PHY_INT8 bY_br;
PHY_INT8 bDeltaX;
PHY_INT8 bDeltaY;
};
struct strucTestCycle
{
PHY_UINT16 wEyeCnt;
PHY_INT8 bNumOfEyeCnt;
PHY_INT8 bPICalEn;
PHY_INT8 bNumOfIgnoreCnt;
};
#define ERRCNT_MAX 128
#define CYCLE_COUNT_MAX 15
/// the map resolution is 128 x 128 pts
#define MAX_X 127
#define MAX_Y 127
#define MIN_X 0
#define MIN_Y 0
PHY_INT32 u3phy_init(void);
AUTOEXT struct strucScanRegion _rEye1;
AUTOEXT struct strucScanRegion _rEye2;
AUTOEXT struct strucTestCycle _rTestCycle;
AUTOEXT PHY_UINT8 _bXcurr;
AUTOEXT PHY_UINT8 _bYcurr;
AUTOEXT enumScanDir _eScanDir;
AUTOEXT PHY_INT8 _fgXChged;
AUTOEXT PHY_INT8 _bPIResult;
/* use local variable instead to save memory use */
#if 0
AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
#endif
/***********************************/
#endif

115
target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.c Normal file
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#include "xhci-mtk.h"
#include "xhci-mtk-power.h"
#include "xhci.h"
#include <linux/kernel.h> /* printk() */
#include <linux/slab.h>
#include <linux/delay.h>
static int g_num_u3_port;
static int g_num_u2_port;
void enableXhciAllPortPower(struct xhci_hcd *xhci){
int i;
u32 port_id, temp;
u32 __iomem *addr;
g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
for(i=1; i<=g_num_u3_port; i++){
port_id=i;
addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
temp = xhci_readl(xhci, addr);
temp = xhci_port_state_to_neutral(temp);
temp |= PORT_POWER;
xhci_writel(xhci, temp, addr);
}
for(i=1; i<=g_num_u2_port; i++){
port_id=i+g_num_u3_port;
addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
temp = xhci_readl(xhci, addr);
temp = xhci_port_state_to_neutral(temp);
temp |= PORT_POWER;
xhci_writel(xhci, temp, addr);
}
}
void enableAllClockPower(){
int i;
u32 temp;
g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
//2. Enable xHC
writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
//1. Enable target ports
for(i=0; i<g_num_u3_port; i++){
temp = readl(SSUSB_U3_CTRL(i));
temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
writel(temp, SSUSB_U3_CTRL(i));
}
for(i=0; i<g_num_u2_port; i++){
temp = readl(SSUSB_U2_CTRL(i));
temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
writel(temp, SSUSB_U2_CTRL(i));
}
msleep(100);
}
//(X)disable clock/power of a port
//(X)if all ports are disabled, disable IP ctrl power
//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
//and IP could be disable if suspended.
//If doesn't not disable all ports at first, the IP clock/power will never be disabled
//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
//port_index: port number
//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
void disablePortClockPower(void){
int i;
u32 temp;
g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
for(i=0; i<g_num_u3_port; i++){
temp = readl(SSUSB_U3_CTRL(i));
temp = temp | (SSUSB_U3_PORT_PDN);
writel(temp, SSUSB_U3_CTRL(i));
}
for(i=0; i<g_num_u2_port; i++){
temp = readl(SSUSB_U2_CTRL(i));
temp = temp | (SSUSB_U2_PORT_PDN);
writel(temp, SSUSB_U2_CTRL(i));
}
writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
}
//if IP ctrl power is disabled, enable it
//enable clock/power of a port
//port_index: port number
//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
void enablePortClockPower(int port_index, int port_rev){
int i;
u32 temp;
writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
if(port_rev == 0x3){
temp = readl(SSUSB_U3_CTRL(port_index));
temp = temp & (~SSUSB_U3_PORT_PDN);
writel(temp, SSUSB_U3_CTRL(port_index));
}
else if(port_rev == 0x2){
temp = readl(SSUSB_U2_CTRL(port_index));
temp = temp & (~SSUSB_U2_PORT_PDN);
writel(temp, SSUSB_U2_CTRL(port_index));
}
}

13
target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.h Normal file
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#ifndef _XHCI_MTK_POWER_H
#define _XHCI_MTK_POWER_H
#include <linux/usb.h>
#include "xhci.h"
#include "xhci-mtk.h"
void enableXhciAllPortPower(struct xhci_hcd *xhci);
void enableAllClockPower(void);
void disablePortClockPower(void);
void enablePortClockPower(int port_index, int port_rev);
#endif

608
target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.c Normal file
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#include "xhci-mtk-scheduler.h"
#include <linux/kernel.h> /* printk() */
static struct sch_ep **ss_out_eps[MAX_EP_NUM];
static struct sch_ep **ss_in_eps[MAX_EP_NUM];
static struct sch_ep **hs_eps[MAX_EP_NUM]; //including tt isoc
static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
int mtk_xhci_scheduler_init(void){
int i;
for(i=0; i<MAX_EP_NUM; i++){
ss_out_eps[i] = NULL;
}
for(i=0; i<MAX_EP_NUM; i++){
ss_in_eps[i] = NULL;
}
for(i=0; i<MAX_EP_NUM; i++){
hs_eps[i] = NULL;
}
for(i=0; i<MAX_EP_NUM; i++){
tt_intr_eps[i] = NULL;
}
return 0;
}
int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
, int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
, int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
struct sch_ep **ep_array;
int i;
if(is_in && dev_speed == USB_SPEED_SUPER ){
ep_array = (struct sch_ep **)ss_in_eps;
}
else if(dev_speed == USB_SPEED_SUPER){
ep_array = (struct sch_ep **)ss_out_eps;
}
else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
ep_array = (struct sch_ep **)hs_eps;
}
else{
ep_array = (struct sch_ep **)tt_intr_eps;
}
for(i=0; i<MAX_EP_NUM; i++){
if(ep_array[i] == NULL){
tmp_ep->dev_speed = dev_speed;
tmp_ep->isTT = isTT;
tmp_ep->is_in = is_in;
tmp_ep->ep_type = ep_type;
tmp_ep->maxp = maxp;
tmp_ep->interval = interval;
tmp_ep->burst = burst;
tmp_ep->mult = mult;
tmp_ep->offset = offset;
tmp_ep->repeat = repeat;
tmp_ep->pkts = pkts;
tmp_ep->cs_count = cs_count;
tmp_ep->burst_mode = burst_mode;
tmp_ep->bw_cost = bw_cost;
tmp_ep->ep = ep;
ep_array[i] = tmp_ep;
return SCH_SUCCESS;
}
}
return SCH_FAIL;
}
int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
, int td_size){
int i, j, k;
int bw_required[3];
int final_bw_required;
int bw_required_per_repeat;
int tmp_bw_required;
struct sch_ep *cur_sch_ep;
struct sch_ep **ep_array;
int cur_offset;
int cur_ep_offset;
int tmp_offset;
int tmp_interval;
int ep_offset;
int ep_interval;
int ep_repeat;
int ep_mult;
if(is_in){
ep_array = (struct sch_ep **)ss_in_eps;
}
else{
ep_array = (struct sch_ep **)ss_out_eps;
}
bw_required[0] = 0;
bw_required[1] = 0;
bw_required[2] = 0;
if(repeat == 0){
final_bw_required = 0;
for(i=0; i<MAX_EP_NUM; i++){
cur_sch_ep = ep_array[i];
if(cur_sch_ep == NULL){
continue;
}
ep_interval = cur_sch_ep->interval;
ep_offset = cur_sch_ep->offset;
if(cur_sch_ep->repeat == 0){
if(ep_interval >= interval){
tmp_offset = ep_offset + ep_interval - offset;
tmp_interval = interval;
}
else{
tmp_offset = offset + interval - ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset % tmp_interval == 0){
final_bw_required += cur_sch_ep->bw_cost;
}
}
else{
ep_repeat = cur_sch_ep->repeat;
ep_mult = cur_sch_ep->mult;
for(k=0; k<=ep_mult; k++){
cur_ep_offset = ep_offset+(k*ep_mult);
if(ep_interval >= interval){
tmp_offset = cur_ep_offset + ep_interval - offset;
tmp_interval = interval;
}
else{
tmp_offset = offset + interval - cur_ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset % tmp_interval == 0){
final_bw_required += cur_sch_ep->bw_cost;
break;
}
}
}
}
final_bw_required += td_size;
}
else{
bw_required_per_repeat = maxp * (burst+1);
for(j=0; j<=mult; j++){
tmp_bw_required = 0;
cur_offset = offset+(j*repeat);
for(i=0; i<MAX_EP_NUM; i++){
cur_sch_ep = ep_array[i];
if(cur_sch_ep == NULL){
continue;
}
ep_interval = cur_sch_ep->interval;
ep_offset = cur_sch_ep->offset;
if(cur_sch_ep->repeat == 0){
if(ep_interval >= interval){
tmp_offset = ep_offset + ep_interval - cur_offset;
tmp_interval = interval;
}
else{
tmp_offset = cur_offset + interval - ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset % tmp_interval == 0){
tmp_bw_required += cur_sch_ep->bw_cost;
}
}
else{
ep_repeat = cur_sch_ep->repeat;
ep_mult = cur_sch_ep->mult;
for(k=0; k<=ep_mult; k++){
cur_ep_offset = ep_offset+(k*ep_repeat);
if(ep_interval >= interval){
tmp_offset = cur_ep_offset + ep_interval - cur_offset;
tmp_interval = interval;
}
else{
tmp_offset = cur_offset + interval - cur_ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset % tmp_interval == 0){
tmp_bw_required += cur_sch_ep->bw_cost;
break;
}
}
}
}
bw_required[j] = tmp_bw_required;
}
final_bw_required = SS_BW_BOUND;
for(j=0; j<=mult; j++){
if(bw_required[j] < final_bw_required){
final_bw_required = bw_required[j];
}
}
final_bw_required += bw_required_per_repeat;
}
return final_bw_required;
}
int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
int i;
int bw_required;
struct sch_ep *cur_sch_ep;
int tmp_offset;
int tmp_interval;
int ep_offset;
int ep_interval;
int cur_tt_isoc_interval; //for isoc tt check
bw_required = 0;
for(i=0; i<MAX_EP_NUM; i++){
cur_sch_ep = (struct sch_ep *)hs_eps[i];
if(cur_sch_ep == NULL){
continue;
}
ep_offset = cur_sch_ep->offset;
ep_interval = cur_sch_ep->interval;
if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
cur_tt_isoc_interval = ep_interval<<3;
if(ep_interval >= interval){
tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
tmp_interval = interval;
}
else{
tmp_offset = offset + interval - ep_offset;
tmp_interval = cur_tt_isoc_interval;
}
if(cur_sch_ep->is_in){
if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
bw_required += 188;
}
}
else{
if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
bw_required += 188;
}
}
}
else{
if(ep_interval >= interval){
tmp_offset = ep_offset + ep_interval - offset;
tmp_interval = interval;
}
else{
tmp_offset = offset + interval - ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset%tmp_interval == 0){
bw_required += cur_sch_ep->bw_cost;
}
}
}
bw_required += td_size;
return bw_required;
}
int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
char is_cs;
int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
int bw_required, max_bw;
int ss_cs_count;
int cs_mframe;
int max_frame;
int i,j;
struct sch_ep *cur_sch_ep;
int ep_offset;
int ep_interval;
int ep_cs_count;
int tt_isoc_interval; //for isoc tt check
int cur_tt_isoc_interval; //for isoc tt check
int tmp_offset;
int tmp_interval;
is_cs = 0;
tt_isoc_interval = interval<<3; //frame to mframe
if(is_in){
is_cs = 1;
}
s_frame = offset/8;
s_mframe = offset%8;
ss_cs_count = (maxp + (188 - 1))/188;
if(is_cs){
cs_mframe = offset%8 + 2 + ss_cs_count;
if (cs_mframe <= 6)
ss_cs_count += 2;
else if (cs_mframe == 7)
ss_cs_count++;
else if (cs_mframe > 8)
return -1;
}
max_bw = 0;
if(is_in){
i=2;
}
for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
bw_required = 0;
for(j=0; j<MAX_EP_NUM; j++){
cur_sch_ep = (struct sch_ep *)hs_eps[j];
if(cur_sch_ep == NULL){
continue;
}
ep_offset = cur_sch_ep->offset;
ep_interval = cur_sch_ep->interval;
if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
//isoc tt
//check if mframe offset overlap
//if overlap, add 188 to the bw
cur_tt_isoc_interval = ep_interval<<3;
if(cur_tt_isoc_interval >= tt_isoc_interval){
tmp_offset = (ep_offset+cur_tt_isoc_interval) - cur_mframe;
tmp_interval = tt_isoc_interval;
}
else{
tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
tmp_interval = cur_tt_isoc_interval;
}
if(cur_sch_ep->is_in){
if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
bw_required += 188;
}
}
else{
if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
bw_required += 188;
}
}
}
else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
//check if mframe
if(ep_interval >= tt_isoc_interval){
tmp_offset = (ep_offset+ep_interval) - cur_mframe;
tmp_interval = tt_isoc_interval;
}
else{
tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset%tmp_interval == 0){
bw_required += cur_sch_ep->bw_cost;
}
}
}
bw_required += 188;
if(bw_required > max_bw){
max_bw = bw_required;
}
}
return max_bw;
}
int count_tt_intr_bw(int interval, int frame_offset){
//check all eps in tt_intr_eps
int ret;
int i,j;
int ep_offset;
int ep_interval;
int tmp_offset;
int tmp_interval;
ret = SCH_SUCCESS;
struct sch_ep *cur_sch_ep;
for(i=0; i<MAX_EP_NUM; i++){
cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
if(cur_sch_ep == NULL){
continue;
}
ep_offset = cur_sch_ep->offset;
ep_interval = cur_sch_ep->interval;
if(ep_interval >= interval){
tmp_offset = ep_offset + ep_interval - frame_offset;
tmp_interval = interval;
}
else{
tmp_offset = frame_offset + interval - ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset%tmp_interval==0){
return SCH_FAIL;
}
}
return SCH_SUCCESS;
}
struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
int i;
struct sch_ep **ep_array;
struct sch_ep *cur_ep;
if (is_in && dev_speed == USB_SPEED_SUPER) {
ep_array = (struct sch_ep **)ss_in_eps;
}
else if (dev_speed == USB_SPEED_SUPER) {
ep_array = (struct sch_ep **)ss_out_eps;
}
else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
ep_array = (struct sch_ep **)hs_eps;
}
else {
ep_array = (struct sch_ep **)tt_intr_eps;
}
for (i = 0; i < MAX_EP_NUM; i++) {
cur_ep = (struct sch_ep *)ep_array[i];
if(cur_ep != NULL && cur_ep->ep == ep){
ep_array[i] = NULL;
return cur_ep;
}
}
return NULL;
}
int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
, int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
mtk_u32 bPkts = 0;
mtk_u32 bCsCount = 0;
mtk_u32 bBm = 1;
mtk_u32 bOffset = 0;
mtk_u32 bRepeat = 0;
int ret;
struct mtk_xhci_ep_ctx *temp_ep_ctx;
int td_size;
int mframe_idx, frame_idx;
int bw_cost;
int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
int cur_offset, cs_mframe;
int break_out;
int frame_interval;
printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
, interval, burst, mult, ep, ep_ctx, sch_ep);
if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
frame_interval = interval >> 3;
for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
printk(KERN_ERR "check OK............\n");
bOffset = frame_idx<<3;
bPkts = 1;
bCsCount = 3;
bw_cost = maxp;
bRepeat = 0;
if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
, bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
return SCH_FAIL;
}
ret = SCH_SUCCESS;
break;
}
}
}
else if(isTT && ep_type == USB_EP_ISOC){
best_bw = HS_BW_BOUND;
best_bw_idx = -1;
cur_bw = 0;
td_size = maxp;
break_out = 0;
frame_interval = interval>>3;
for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
for(mframe_idx=0; mframe_idx<8; mframe_idx++){
cur_offset = (frame_idx*8) + mframe_idx;
cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
if(cur_bw > 0 && cur_bw < best_bw){
best_bw_idx = cur_offset;
best_bw = cur_bw;
if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
break_out = 1;
break;
}
}
}
}
if(best_bw_idx == -1){
return SCH_FAIL;
}
else{
bOffset = best_bw_idx;
bPkts = 1;
bCsCount = (maxp + (188 - 1)) / 188;
if(is_in){
cs_mframe = bOffset%8 + 2 + bCsCount;
if (cs_mframe <= 6)
bCsCount += 2;
else if (cs_mframe == 7)
bCsCount++;
}
bw_cost = 188;
bRepeat = 0;
if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
, bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
return SCH_FAIL;
}
ret = SCH_SUCCESS;
}
}
else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
bPkts = 1;
ret = SCH_SUCCESS;
}
else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
bPkts = 1;
ret = SCH_SUCCESS;
}
else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
best_bw = HS_BW_BOUND;
best_bw_idx = -1;
cur_bw = 0;
td_size = maxp*(burst+1);
for(cur_offset = 0; cur_offset<interval; cur_offset++){
cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
if(cur_bw > 0 && cur_bw < best_bw){
best_bw_idx = cur_offset;
best_bw = cur_bw;
if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
break;
}
}
}
if(best_bw_idx == -1){
return SCH_FAIL;
}
else{
bOffset = best_bw_idx;
bPkts = burst + 1;
bCsCount = 0;
bw_cost = td_size;
bRepeat = 0;
if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
, bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
return SCH_FAIL;
}
ret = SCH_SUCCESS;
}
}
else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
best_bw = SS_BW_BOUND;
best_bw_idx = -1;
cur_bw = 0;
td_size = maxp * (mult+1) * (burst+1);
if(mult == 0){
max_repeat = 0;
}
else{
max_repeat = (interval-1)/(mult+1);
}
break_out = 0;
for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
for(repeat = max_repeat; repeat >= 0; repeat--){
cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
, repeat, td_size);
printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
, frame_idx, repeat, td_size, cur_bw);
if(cur_bw > 0 && cur_bw < best_bw){
best_bw_idx = frame_idx;
best_bw_repeat = repeat;
best_bw = cur_bw;
if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
break_out = 1;
break;
}
}
}
}
printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
if(best_bw_idx == -1){
return SCH_FAIL;
}
else{
bOffset = best_bw_idx;
bCsCount = 0;
bRepeat = best_bw_repeat;
if(bRepeat == 0){
bw_cost = (burst+1)*(mult+1)*maxp;
bPkts = (burst+1)*(mult+1);
}
else{
bw_cost = (burst+1)*maxp;
bPkts = (burst+1);
}
if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
, bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
return SCH_FAIL;
}
ret = SCH_SUCCESS;
}
}
else{
bPkts = 1;
ret = SCH_SUCCESS;
}
if(ret == SCH_SUCCESS){
temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
return SCH_SUCCESS;
}
else{
return SCH_FAIL;
}
}

77
target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.h Normal file
View File

@@ -0,0 +1,77 @@
#ifndef _XHCI_MTK_SCHEDULER_H
#define _XHCI_MTK_SCHEDULER_H
#define MTK_SCH_NEW 1
#define SCH_SUCCESS 1
#define SCH_FAIL 0
#define MAX_EP_NUM 64
#define SS_BW_BOUND 51000
#define HS_BW_BOUND 6144
#define USB_EP_CONTROL 0
#define USB_EP_ISOC 1
#define USB_EP_BULK 2
#define USB_EP_INT 3
#define USB_SPEED_LOW 1
#define USB_SPEED_FULL 2
#define USB_SPEED_HIGH 3
#define USB_SPEED_SUPER 5
/* mtk scheduler bitmasks */
#define BPKTS(p) ((p) & 0x3f)
#define BCSCOUNT(p) (((p) & 0x7) << 8)
#define BBM(p) ((p) << 11)
#define BOFFSET(p) ((p) & 0x3fff)
#define BREPEAT(p) (((p) & 0x7fff) << 16)
#if 1
typedef unsigned int mtk_u32;
typedef unsigned long long mtk_u64;
#endif
#define NULL ((void *)0)
struct mtk_xhci_ep_ctx {
mtk_u32 ep_info;
mtk_u32 ep_info2;
mtk_u64 deq;
mtk_u32 tx_info;
/* offset 0x14 - 0x1f reserved for HC internal use */
mtk_u32 reserved[3];
};
struct sch_ep
{
//device info
int dev_speed;
int isTT;
//ep info
int is_in;
int ep_type;
int maxp;
int interval;
int burst;
int mult;
//scheduling info
int offset;
int repeat;
int pkts;
int cs_count;
int burst_mode;
//other
int bw_cost; //bandwidth cost in each repeat; including overhead
mtk_u32 *ep; //address of usb_endpoint pointer
};
int mtk_xhci_scheduler_init(void);
int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
, int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
#endif

265
target/linux/ramips/files/drivers/usb/host/xhci-mtk.c Normal file
View File

@@ -0,0 +1,265 @@
#include "xhci-mtk.h"
#include "xhci-mtk-power.h"
#include "xhci.h"
#include "mtk-phy.h"
#ifdef CONFIG_C60802_SUPPORT
#include "mtk-phy-c60802.h"
#endif
#include "xhci-mtk-scheduler.h"
#include <linux/kernel.h> /* printk() */
#include <linux/slab.h>
#include <linux/delay.h>
#include <asm/uaccess.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
void setInitialReg(void )
{
__u32 __iomem *addr;
u32 temp;
/* set SSUSB DMA burst size to 128B */
addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
temp = SSUSB_HDMA_CFG_MT7621_VALUE;
writel(temp, addr);
/* extend U3 LTSSM Polling.LFPS timeout value */
addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
writel(temp, addr);
/* EOF */
addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
temp = SYNC_HS_EOF_VALUE;
writel(temp, addr);
#if defined (CONFIG_PERIODIC_ENP)
/* HSCH_CFG1: SCH2_FIFO_DEPTH */
addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
temp = readl(addr);
temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
writel(temp, addr);
#endif
/* Doorbell handling */
addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
temp = 0x1;
writel(temp, addr);
/* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
/* Port 0 */
addr = U2_PHY_BASE + U2_PHYD_CR1;
temp = readl(addr);
temp &= ~(0x3 << 18);
temp |= (1 << 18);
writel(temp, addr);
/* Port 1 */
addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
temp = readl(addr);
temp &= ~(0x3 << 18);
temp |= (1 << 18);
writel(temp, addr);
}
void setLatchSel(void){
__u32 __iomem *latch_sel_addr;
u32 latch_sel_value;
latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
writel(latch_sel_value, latch_sel_addr);
}
void reinitIP(void){
__u32 __iomem *ip_reset_addr;
u32 ip_reset_value;
enableAllClockPower();
mtk_xhci_scheduler_init();
}
void dbg_prb_out(void){
mtk_probe_init(0x0f0f0f0f);
mtk_probe_out(0xffffffff);
mtk_probe_out(0x01010101);
mtk_probe_out(0x02020202);
mtk_probe_out(0x04040404);
mtk_probe_out(0x08080808);
mtk_probe_out(0x10101010);
mtk_probe_out(0x20202020);
mtk_probe_out(0x40404040);
mtk_probe_out(0x80808080);
mtk_probe_out(0x55555555);
mtk_probe_out(0xaaaaaaaa);
}
///////////////////////////////////////////////////////////////////////////////
#define RET_SUCCESS 0
#define RET_FAIL 1
static int dbg_u3w(int argc, char**argv)
{
int u4TimingValue;
char u1TimingValue;
int u4TimingAddress;
if (argc<3)
{
printk(KERN_ERR "Arg: address value\n");
return RET_FAIL;
}
u3phy_init();
u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
u1TimingValue = u4TimingValue & 0xff;
/* access MMIO directly */
writel(u1TimingValue, u4TimingAddress);
printk(KERN_ERR "Write done\n");
return RET_SUCCESS;
}
static int dbg_u3r(int argc, char**argv)
{
char u1ReadTimingValue;
int u4TimingAddress;
if (argc<2)
{
printk(KERN_ERR "Arg: address\n");
return 0;
}
u3phy_init();
mdelay(500);
u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
/* access MMIO directly */
u1ReadTimingValue = readl(u4TimingAddress);
printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
return 0;
}
static int dbg_u3init(int argc, char**argv)
{
int ret;
ret = u3phy_init();
printk(KERN_ERR "phy registers and operations initial done\n");
if(u3phy_ops->u2_slew_rate_calibration){
u3phy_ops->u2_slew_rate_calibration(u3phy);
}
else{
printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
}
if(u3phy_ops->init(u3phy) == PHY_TRUE)
return RET_SUCCESS;
return RET_FAIL;
}
void dbg_setU1U2(int argc, char**argv){
struct xhci_hcd *xhci;
int u1_value;
int u2_value;
u32 port_id, temp;
u32 __iomem *addr;
if (argc<3)
{
printk(KERN_ERR "Arg: u1value u2value\n");
return RET_FAIL;
}
u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
addr = (SSUSB_U3_XHCI_BASE + 0x424);
temp = readl(addr);
temp = temp & (~(0x0000ffff));
temp = temp | u1_value | (u2_value<<8);
writel(temp, addr);
}
///////////////////////////////////////////////////////////////////////////////
int call_function(char *buf)
{
int i;
int argc;
char *argv[80];
argc = 0;
do
{
argv[argc] = strsep(&buf, " ");
printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
argc++;
} while (buf);
if (!strcmp("dbg.r", argv[0]))
dbg_prb_out();
else if (!strcmp("dbg.u3w", argv[0]))
dbg_u3w(argc, argv);
else if (!strcmp("dbg.u3r", argv[0]))
dbg_u3r(argc, argv);
else if (!strcmp("dbg.u3i", argv[0]))
dbg_u3init(argc, argv);
else if (!strcmp("pw.u1u2", argv[0]))
dbg_setU1U2(argc, argv);
return 0;
}
long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
char w_buf[200];
char r_buf[200] = "this is a test";
int len = 200;
switch (cmd) {
case IOCTL_READ:
copy_to_user((char *) arg, r_buf, len);
printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
break;
case IOCTL_WRITE:
copy_from_user(w_buf, (char *) arg, len);
printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
//invoke function
return call_function(w_buf);
break;
default:
return -ENOTTY;
}
return len;
}
int xhci_mtk_test_open(struct inode *inode, struct file *file)
{
printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
return 0;
}
int xhci_mtk_test_release(struct inode *inode, struct file *file)
{
printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
return 0;
}
ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
{
printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
return 0;
}
ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
{
printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
return 0;
}

120
target/linux/ramips/files/drivers/usb/host/xhci-mtk.h Normal file
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@@ -0,0 +1,120 @@
#ifndef _XHCI_MTK_H
#define _XHCI_MTK_H
#include <linux/usb.h>
#include "xhci.h"
#define SSUSB_U3_XHCI_BASE 0xBE1C0000
#define SSUSB_U3_MAC_BASE 0xBE1C2400
#define SSUSB_U3_SYS_BASE 0xBE1C2600
#define SSUSB_U2_SYS_BASE 0xBE1C3400
#define SSUB_SIF_SLV_TOP 0xBE1D0000
#define SIFSLV_IPPC (SSUB_SIF_SLV_TOP + 0x700)
#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
#define U3_PIPE_LATCH_TX 0
#define U3_PIPE_LATCH_RX 0
#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
#define U3_REF_CK_PAR 0xb0
#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
#define U3_RX_UX_EXIT_LFPS_REF 3
#define U3_REF_CK_VAL 10
#define U3_TIMING_PULSE_CTRL 0xb4
#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
#define USB20_TIMING_PARAMETER 0x40
#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
#define LINK_PM_TIMER 0x8
#define PM_LC_TIMEOUT_VALUE 3
#define XHCI_IMOD 0x624
#define XHCI_IMOD_MT7621_VALUE 0x10
#define SSUSB_HDMA_CFG 0x950
#define SSUSB_HDMA_CFG_MT7621_VALUE 0x10E0E0C
#define U3_LTSSM_TIMING_PARAMETER3 0x2514
#define U3_LTSSM_TIMING_PARAMETER3_VALUE 0x3E8012C
#define U2_PHYD_CR1 0x64
#define SSUSB_IP_SPAR0 0xC8
#define SYNC_HS_EOF 0x938
#define SYNC_HS_EOF_VALUE 0x201F3
#define HSCH_CFG1 0x960
#define SCH2_FIFO_DEPTH_OFFSET 16
#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
#define SSUSB_IP_SW_RST (1<<0)
#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
#define SSUSB_IP_PDN (1<<0)
#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
#define SSUSB_U3_PORT_DIS (1<<0)
#define SSUSB_U3_PORT_PDN (1<<1)
#define SSUSB_U3_PORT_HOST_SEL (1<<2)
#define SSUSB_U3_PORT_CKBG_EN (1<<3)
#define SSUSB_U3_PORT_MAC_RST (1<<4)
#define SSUSB_U3_PORT_PHYD_RST (1<<5)
#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
#define SSUSB_U2_PORT_DIS (1<<0)
#define SSUSB_U2_PORT_PDN (1<<1)
#define SSUSB_U2_PORT_HOST_SEL (1<<2)
#define SSUSB_U2_PORT_CKBG_EN (1<<3)
#define SSUSB_U2_PORT_MAC_RST (1<<4)
#define SSUSB_U2_PORT_PHYD_RST (1<<5)
#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
#define XHCI_MTK_TEST_MAJOR 234
#define DEVICE_NAME "xhci_mtk_test"
#define CLI_MAGIC 'CLI'
#define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
#define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
void reinitIP(void);
void setInitialReg(void);
void dbg_prb_out(void);
int call_function(char *buf);
long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
int xhci_mtk_test_open(struct inode *inode, struct file *file);
int xhci_mtk_test_release(struct inode *inode, struct file *file);
ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
/*
mediatek probe out
*/
/************************************************************************************/
#define SW_PRB_OUT_ADDR (SIFSLV_IPPC+0xc0)
#define PRB_MODULE_SEL_ADDR (SIFSLV_IPPC+0xbc)
static inline void mtk_probe_init(const u32 byte){
__u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
writel(byte, ptr);
}
static inline void mtk_probe_out(const u32 value){
__u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
writel(value, ptr);
}
static inline u32 mtk_probe_value(void){
__u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
return readl(ptr);
}
#endif