forked from Ivasoft/openwrt
ipq40xx: move DSA and ethernet driver to 5.15 specific directory
As a preparation to move to 6.1, we need to move the DSA and ethernet drivers to a 5.15 specific directory as 6.1 will use the latest patchset that was sent upstream which is too hard to backport to 5.15. Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko
committed by
Christian Marangi
Christian Marangi
parent
d2ce3a61aa
commit
9bfbdfa778
File diff suppressed because it is too large
Load Diff
@@ -1,293 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef __QCA8K_H
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#define __QCA8K_H
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#include <linux/regmap.h>
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#define QCA8K_NUM_PORTS 6
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#define QCA8K_CPU_PORT 0
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#define QCA8K_MAX_MTU 9000
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#define QCA8K_BUSY_WAIT_TIMEOUT 2000
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#define QCA8K_NUM_FDB_RECORDS 2048
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#define QCA8K_PORT_VID_DEF 1
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/* Global control registers */
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#define QCA8K_REG_MASK_CTRL 0x000
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#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
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#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
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#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
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#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
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#define QCA8K_REG_RGMII_CTRL 0x004
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#define QCA8K_RGMII_CTRL_RGMII_RXC GENMASK(1, 0)
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#define QCA8K_RGMII_CTRL_RGMII_TXC GENMASK(9, 8)
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/* Some kind of CLK selection
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* 0: gcc_ess_dly2ns
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* 1: gcc_ess_clk
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*/
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#define QCA8K_RGMII_CTRL_CLK BIT(10)
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#define QCA8K_RGMII_CTRL_DELAY_RMII0 GENMASK(17, 16)
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#define QCA8K_RGMII_CTRL_INVERT_RMII0_REF_CLK BIT(18)
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#define QCA8K_RGMII_CTRL_DELAY_RMII1 GENMASK(20, 19)
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#define QCA8K_RGMII_CTRL_INVERT_RMII1_REF_CLK BIT(21)
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#define QCA8K_RGMII_CTRL_INVERT_RMII0_MASTER_EN BIT(24)
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#define QCA8K_RGMII_CTRL_INVERT_RMII1_MASTER_EN BIT(25)
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#define QCA8K_REG_MODULE_EN 0x030
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#define QCA8K_MODULE_EN_MIB BIT(0)
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#define QCA8K_REG_MIB 0x034
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#define QCA8K_MIB_FLUSH BIT(24)
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#define QCA8K_MIB_CPU_KEEP BIT(20)
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#define QCA8K_MIB_BUSY BIT(17)
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#define QCA8K_GOL_MAC_ADDR0 0x60
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#define QCA8K_GOL_MAC_ADDR1 0x64
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#define QCA8K_MAX_FRAME_SIZE 0x78
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#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
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#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
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#define QCA8K_PORT_STATUS_SPEED_10 0
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#define QCA8K_PORT_STATUS_SPEED_100 0x1
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#define QCA8K_PORT_STATUS_SPEED_1000 0x2
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#define QCA8K_PORT_STATUS_TXMAC BIT(2)
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#define QCA8K_PORT_STATUS_RXMAC BIT(3)
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#define QCA8K_PORT_STATUS_TXFLOW BIT(4)
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#define QCA8K_PORT_STATUS_RXFLOW BIT(5)
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#define QCA8K_PORT_STATUS_DUPLEX BIT(6)
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#define QCA8K_PORT_STATUS_LINK_UP BIT(8)
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#define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
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#define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
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#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
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#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
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#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
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#define QCA8K_PORT_HDR_CTRL_RX_S 2
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#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
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#define QCA8K_PORT_HDR_CTRL_TX_S 0
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#define QCA8K_PORT_HDR_CTRL_ALL 2
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#define QCA8K_PORT_HDR_CTRL_MGMT 1
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#define QCA8K_PORT_HDR_CTRL_NONE 0
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#define QCA8K_REG_SGMII_CTRL 0x0e0
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#define QCA8K_SGMII_EN_PLL BIT(1)
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#define QCA8K_SGMII_EN_RX BIT(2)
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#define QCA8K_SGMII_EN_TX BIT(3)
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#define QCA8K_SGMII_EN_SD BIT(4)
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#define QCA8K_SGMII_CLK125M_DELAY BIT(7)
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#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
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#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
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#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
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#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
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/* EEE control registers */
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#define QCA8K_REG_EEE_CTRL 0x100
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#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
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/* ACL registers */
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#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
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#define QCA8K_PORT_VLAN_CVID(x) (x << 16)
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#define QCA8K_PORT_VLAN_SVID(x) x
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#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
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#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
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#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
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/* Lookup registers */
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#define QCA8K_REG_ATU_DATA0 0x600
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#define QCA8K_ATU_ADDR2_S 24
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#define QCA8K_ATU_ADDR3_S 16
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#define QCA8K_ATU_ADDR4_S 8
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#define QCA8K_REG_ATU_DATA1 0x604
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#define QCA8K_ATU_PORT_M 0x7f
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#define QCA8K_ATU_PORT_S 16
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#define QCA8K_ATU_ADDR0_S 8
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#define QCA8K_REG_ATU_DATA2 0x608
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#define QCA8K_ATU_VID_M 0xfff
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#define QCA8K_ATU_VID_S 8
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#define QCA8K_ATU_STATUS_M 0xf
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#define QCA8K_ATU_STATUS_STATIC 0xf
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#define QCA8K_REG_ATU_FUNC 0x60c
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#define QCA8K_ATU_FUNC_BUSY BIT(31)
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#define QCA8K_ATU_FUNC_PORT_EN BIT(14)
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#define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
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#define QCA8K_ATU_FUNC_FULL BIT(12)
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#define QCA8K_ATU_FUNC_PORT_M 0xf
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#define QCA8K_ATU_FUNC_PORT_S 8
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#define QCA8K_REG_VTU_FUNC0 0x610
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#define QCA8K_VTU_FUNC0_VALID BIT(20)
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#define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
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#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
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#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3
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#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
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#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1
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#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2
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#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3
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#define QCA8K_REG_VTU_FUNC1 0x614
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#define QCA8K_VTU_FUNC1_BUSY BIT(31)
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#define QCA8K_VTU_FUNC1_VID_S 16
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#define QCA8K_VTU_FUNC1_FULL BIT(4)
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#define QCA8K_REG_ATU_CTRL 0x618
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#define QCA8K_ATU_AGE_TIME_MASK GENMASK(15, 0)
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#define QCA8K_ATU_AGE_TIME(x) FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
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#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
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#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
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#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
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#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
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#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
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#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
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#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
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#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
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#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
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#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8)
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#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
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#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8)
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#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8)
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#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8)
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#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
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#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
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#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
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#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
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#define QCA8K_PORT_LOOKUP_LOOPBACK BIT(21)
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#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
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#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16)
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#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16)
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#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0)
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#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0)
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#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20)
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#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24)
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#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24)
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#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
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#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
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#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
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#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
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#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
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#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
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#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
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/* Pkt edit registers */
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#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
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/* L3 registers */
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#define QCA8K_HROUTER_CONTROL 0xe00
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#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)
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#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16
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#define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1
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#define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
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#define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
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#define QCA8K_HNAT_CONTROL 0xe38
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/* MIB registers */
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#define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
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/* IPQ4019 PSGMII PHY registers */
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#define PSGMIIPHY_MODE_CONTROL 0x1b4
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#define PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M BIT(0)
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#define PSGMIIPHY_TX_CONTROL 0x288
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#define PSGMIIPHY_TX_CONTROL_MAGIC_VALUE 0x8380
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#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1 0x9c
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#define PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART BIT(14)
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#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2 0xa0
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#define PSGMIIPHY_REG_PLL_VCO_CALIB_READY BIT(0)
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#define QCA8K_PSGMII_CALB_NUM 100
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#define MII_QCA8075_SSTATUS 0x11
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#define QCA8075_PHY_SPEC_STATUS_LINK BIT(10)
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#define QCA8075_MMD7_CRC_AND_PKTS_COUNT 0x8029
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#define QCA8075_MMD7_PKT_GEN_PKT_NUMB 0x8021
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#define QCA8075_MMD7_PKT_GEN_PKT_SIZE 0x8062
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#define QCA8075_MMD7_PKT_GEN_CTRL 0x8020
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#define QCA8075_MMD7_CNT_SELFCLR BIT(1)
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#define QCA8075_MMD7_CNT_FRAME_CHK_EN BIT(0)
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#define QCA8075_MMD7_PKT_GEN_START BIT(13)
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#define QCA8075_MMD7_PKT_GEN_INPROGR BIT(15)
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#define QCA8075_MMD7_IG_FRAME_RECV_CNT_HI 0x802a
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#define QCA8075_MMD7_IG_FRAME_RECV_CNT_LO 0x802b
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#define QCA8075_MMD7_IG_FRAME_ERR_CNT 0x802c
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#define QCA8075_MMD7_EG_FRAME_RECV_CNT_HI 0x802d
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#define QCA8075_MMD7_EG_FRAME_RECV_CNT_LO 0x802e
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#define QCA8075_MMD7_EG_FRAME_ERR_CNT 0x802f
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#define QCA8075_MMD7_MDIO_BRDCST_WRITE 0x8028
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#define QCA8075_MMD7_MDIO_BRDCST_WRITE_EN BIT(15)
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#define QCA8075_MDIO_BRDCST_PHY_ADDR 0x1f
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#define QCA8075_PKT_GEN_PKTS_COUNT 4096
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enum {
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QCA8K_PORT_SPEED_10M = 0,
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QCA8K_PORT_SPEED_100M = 1,
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QCA8K_PORT_SPEED_1000M = 2,
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QCA8K_PORT_SPEED_ERR = 3,
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};
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enum qca8k_fdb_cmd {
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QCA8K_FDB_FLUSH = 1,
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QCA8K_FDB_LOAD = 2,
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QCA8K_FDB_PURGE = 3,
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QCA8K_FDB_FLUSH_PORT = 5,
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QCA8K_FDB_NEXT = 6,
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QCA8K_FDB_SEARCH = 7,
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};
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enum qca8k_vlan_cmd {
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QCA8K_VLAN_FLUSH = 1,
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QCA8K_VLAN_LOAD = 2,
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QCA8K_VLAN_PURGE = 3,
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QCA8K_VLAN_REMOVE_PORT = 4,
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QCA8K_VLAN_NEXT = 5,
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QCA8K_VLAN_READ = 6,
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};
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struct ar8xxx_port_status {
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int enabled;
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};
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struct qca8k_priv {
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struct regmap *regmap;
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struct mii_bus *bus;
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struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
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struct dsa_switch *ds;
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struct mutex reg_mutex;
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struct device *dev;
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struct dsa_switch_ops ops;
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unsigned int port_mtu[QCA8K_NUM_PORTS];
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/* IPQ4019 specific */
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struct regmap *psgmii;
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bool psgmii_calibrated;
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struct phy_device *psgmii_ethphy;
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};
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struct qca8k_mib_desc {
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unsigned int size;
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unsigned int offset;
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const char *name;
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};
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struct qca8k_fdb {
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u16 vid;
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u8 port_mask;
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u8 aging;
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u8 mac[6];
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};
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#endif /* __QCA8K_H */
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@@ -1,8 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Makefile for the IPQ ESS driver
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#
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obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipq_ess.o
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ipq_ess-objs := ipqess.o ipqess_ethtool.o
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File diff suppressed because it is too large
Load Diff
@@ -1,530 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0 OR ISC)
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/* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
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* Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
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* Copyright (c) 2018 - 2019, Christian Lamparter <chunkeey@gmail.com>
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* Copyright (c) 2020 - 2021, Gabor Juhos <j4g8y7@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all copies.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
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* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _IPQESS_H_
|
||||
#define _IPQESS_H_
|
||||
|
||||
#define IPQESS_NETDEV_QUEUES 4
|
||||
|
||||
#define IPQESS_TPD_EOP_SHIFT 31
|
||||
|
||||
#define IPQESS_PORT_ID_SHIFT 12
|
||||
#define IPQESS_PORT_ID_MASK 0x7
|
||||
|
||||
/* tpd word 3 bit 18-28 */
|
||||
#define IPQESS_TPD_PORT_BITMAP_SHIFT 18
|
||||
|
||||
#define IPQESS_TPD_FROM_CPU_SHIFT 25
|
||||
|
||||
#define IPQESS_RX_RING_SIZE 128
|
||||
#define IPQESS_RX_HEAD_BUFF_SIZE 1540
|
||||
#define IPQESS_TX_RING_SIZE 128
|
||||
#define IPQESS_MAX_RX_QUEUE 8
|
||||
#define IPQESS_MAX_TX_QUEUE 16
|
||||
|
||||
|
||||
/* Configurations */
|
||||
#define IPQESS_INTR_CLEAR_TYPE 0
|
||||
#define IPQESS_INTR_SW_IDX_W_TYPE 0
|
||||
#define IPQESS_FIFO_THRESH_TYPE 0
|
||||
#define IPQESS_RSS_TYPE 0
|
||||
#define IPQESS_RX_IMT 0x0020
|
||||
#define IPQESS_TX_IMT 0x0050
|
||||
#define IPQESS_TPD_BURST 5
|
||||
#define IPQESS_TXF_BURST 0x100
|
||||
#define IPQESS_RFD_BURST 8
|
||||
#define IPQESS_RFD_THR 16
|
||||
#define IPQESS_RFD_LTHR 0
|
||||
|
||||
/* Flags used in transmit direction */
|
||||
#define IPQESS_DESC_LAST 0x1
|
||||
#define IPQESS_DESC_SINGLE 0x2
|
||||
#define IPQESS_DESC_PAGE 0x4
|
||||
|
||||
struct ipqesstool_statistics {
|
||||
u32 tx_q0_pkt;
|
||||
u32 tx_q1_pkt;
|
||||
u32 tx_q2_pkt;
|
||||
u32 tx_q3_pkt;
|
||||
u32 tx_q4_pkt;
|
||||
u32 tx_q5_pkt;
|
||||
u32 tx_q6_pkt;
|
||||
u32 tx_q7_pkt;
|
||||
u32 tx_q8_pkt;
|
||||
u32 tx_q9_pkt;
|
||||
u32 tx_q10_pkt;
|
||||
u32 tx_q11_pkt;
|
||||
u32 tx_q12_pkt;
|
||||
u32 tx_q13_pkt;
|
||||
u32 tx_q14_pkt;
|
||||
u32 tx_q15_pkt;
|
||||
u32 tx_q0_byte;
|
||||
u32 tx_q1_byte;
|
||||
u32 tx_q2_byte;
|
||||
u32 tx_q3_byte;
|
||||
u32 tx_q4_byte;
|
||||
u32 tx_q5_byte;
|
||||
u32 tx_q6_byte;
|
||||
u32 tx_q7_byte;
|
||||
u32 tx_q8_byte;
|
||||
u32 tx_q9_byte;
|
||||
u32 tx_q10_byte;
|
||||
u32 tx_q11_byte;
|
||||
u32 tx_q12_byte;
|
||||
u32 tx_q13_byte;
|
||||
u32 tx_q14_byte;
|
||||
u32 tx_q15_byte;
|
||||
u32 rx_q0_pkt;
|
||||
u32 rx_q1_pkt;
|
||||
u32 rx_q2_pkt;
|
||||
u32 rx_q3_pkt;
|
||||
u32 rx_q4_pkt;
|
||||
u32 rx_q5_pkt;
|
||||
u32 rx_q6_pkt;
|
||||
u32 rx_q7_pkt;
|
||||
u32 rx_q0_byte;
|
||||
u32 rx_q1_byte;
|
||||
u32 rx_q2_byte;
|
||||
u32 rx_q3_byte;
|
||||
u32 rx_q4_byte;
|
||||
u32 rx_q5_byte;
|
||||
u32 rx_q6_byte;
|
||||
u32 rx_q7_byte;
|
||||
u32 tx_desc_error;
|
||||
};
|
||||
|
||||
struct ipqess_tx_desc {
|
||||
__le16 len;
|
||||
__le16 svlan_tag;
|
||||
__le32 word1;
|
||||
__le32 addr;
|
||||
__le32 word3;
|
||||
} __aligned(16) __packed;
|
||||
|
||||
struct ipqess_rx_desc {
|
||||
u16 rrd0;
|
||||
u16 rrd1;
|
||||
u16 rrd2;
|
||||
u16 rrd3;
|
||||
u16 rrd4;
|
||||
u16 rrd5;
|
||||
u16 rrd6;
|
||||
u16 rrd7;
|
||||
} __aligned(16) __packed;
|
||||
|
||||
struct ipqess_buf {
|
||||
struct sk_buff *skb;
|
||||
dma_addr_t dma;
|
||||
u32 flags;
|
||||
u16 length;
|
||||
};
|
||||
|
||||
struct ipqess_tx_ring {
|
||||
struct napi_struct napi_tx;
|
||||
u32 idx;
|
||||
int ring_id;
|
||||
struct ipqess *ess;
|
||||
struct netdev_queue *nq;
|
||||
struct ipqess_tx_desc *hw_desc;
|
||||
struct ipqess_buf *buf;
|
||||
dma_addr_t dma;
|
||||
u16 count;
|
||||
u16 head;
|
||||
u16 tail;
|
||||
};
|
||||
|
||||
struct ipqess_rx_ring {
|
||||
struct napi_struct napi_rx;
|
||||
u32 idx;
|
||||
int ring_id;
|
||||
struct ipqess *ess;
|
||||
struct device *ppdev;
|
||||
struct ipqess_rx_desc **hw_desc;
|
||||
struct ipqess_buf *buf;
|
||||
dma_addr_t dma;
|
||||
u16 head;
|
||||
u16 tail;
|
||||
atomic_t refill_count;
|
||||
};
|
||||
|
||||
struct ipqess_rx_ring_refill {
|
||||
struct ipqess_rx_ring *rx_ring;
|
||||
struct work_struct refill_work;
|
||||
};
|
||||
|
||||
#define IPQESS_IRQ_NAME_LEN 32
|
||||
|
||||
struct ipqess {
|
||||
struct net_device *netdev;
|
||||
void __iomem *hw_addr;
|
||||
struct clk *ess_clk;
|
||||
struct reset_control *ess_rst;
|
||||
|
||||
struct ipqess_rx_ring rx_ring[IPQESS_NETDEV_QUEUES];
|
||||
|
||||
struct platform_device *pdev;
|
||||
struct phylink *phylink;
|
||||
struct phylink_config phylink_config;
|
||||
struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
|
||||
|
||||
struct ipqesstool_statistics ipqessstats;
|
||||
spinlock_t stats_lock;
|
||||
struct net_device_stats stats;
|
||||
|
||||
struct ipqess_rx_ring_refill rx_refill[IPQESS_NETDEV_QUEUES];
|
||||
u32 tx_irq[IPQESS_MAX_TX_QUEUE];
|
||||
char tx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
|
||||
u32 rx_irq[IPQESS_MAX_RX_QUEUE];
|
||||
char rx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
|
||||
};
|
||||
|
||||
static inline void build_test(void)
|
||||
{
|
||||
struct ipqess *ess;
|
||||
BUILD_BUG_ON(ARRAY_SIZE(ess->rx_ring) != ARRAY_SIZE(ess->rx_refill));
|
||||
}
|
||||
|
||||
void ipqess_set_ethtool_ops(struct net_device *netdev);
|
||||
void ipqess_update_hw_stats(struct ipqess *ess);
|
||||
|
||||
/* register definition */
|
||||
#define IPQESS_REG_MAS_CTRL 0x0
|
||||
#define IPQESS_REG_TIMEOUT_CTRL 0x004
|
||||
#define IPQESS_REG_DBG0 0x008
|
||||
#define IPQESS_REG_DBG1 0x00C
|
||||
#define IPQESS_REG_SW_CTRL0 0x100
|
||||
#define IPQESS_REG_SW_CTRL1 0x104
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define IPQESS_REG_RX_ISR 0x200
|
||||
#define IPQESS_REG_TX_ISR 0x208
|
||||
#define IPQESS_REG_MISC_ISR 0x210
|
||||
#define IPQESS_REG_WOL_ISR 0x218
|
||||
|
||||
#define IPQESS_MISC_ISR_RX_URG_Q(x) (1 << x)
|
||||
|
||||
#define IPQESS_MISC_ISR_AXIR_TIMEOUT 0x00000100
|
||||
#define IPQESS_MISC_ISR_AXIR_ERR 0x00000200
|
||||
#define IPQESS_MISC_ISR_TXF_DEAD 0x00000400
|
||||
#define IPQESS_MISC_ISR_AXIW_ERR 0x00000800
|
||||
#define IPQESS_MISC_ISR_AXIW_TIMEOUT 0x00001000
|
||||
|
||||
#define IPQESS_WOL_ISR 0x00000001
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
#define IPQESS_REG_MISC_IMR 0x214
|
||||
#define IPQESS_REG_WOL_IMR 0x218
|
||||
|
||||
#define IPQESS_RX_IMR_NORMAL_MASK 0x1
|
||||
#define IPQESS_TX_IMR_NORMAL_MASK 0x1
|
||||
#define IPQESS_MISC_IMR_NORMAL_MASK 0x80001FFF
|
||||
#define IPQESS_WOL_IMR_NORMAL_MASK 0x1
|
||||
|
||||
/* Edma receive consumer index */
|
||||
#define IPQESS_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
|
||||
|
||||
/* Edma transmit consumer index */
|
||||
#define IPQESS_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
|
||||
|
||||
/* IRQ Moderator Initial Timer Register */
|
||||
#define IPQESS_REG_IRQ_MODRT_TIMER_INIT 0x280
|
||||
#define IPQESS_IRQ_MODRT_TIMER_MASK 0xFFFF
|
||||
#define IPQESS_IRQ_MODRT_RX_TIMER_SHIFT 0
|
||||
#define IPQESS_IRQ_MODRT_TX_TIMER_SHIFT 16
|
||||
|
||||
/* Interrupt Control Register */
|
||||
#define IPQESS_REG_INTR_CTRL 0x284
|
||||
#define IPQESS_INTR_CLR_TYP_SHIFT 0
|
||||
#define IPQESS_INTR_SW_IDX_W_TYP_SHIFT 1
|
||||
#define IPQESS_INTR_CLEAR_TYPE_W1 0
|
||||
#define IPQESS_INTR_CLEAR_TYPE_R 1
|
||||
|
||||
/* RX Interrupt Mask Register */
|
||||
#define IPQESS_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* TX Interrupt mask register */
|
||||
#define IPQESS_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* Load Ptr Register
|
||||
* Software sets this bit after the initialization of the head and tail
|
||||
*/
|
||||
#define IPQESS_REG_TX_SRAM_PART 0x400
|
||||
#define IPQESS_LOAD_PTR_SHIFT 16
|
||||
|
||||
/* TXQ Control Register */
|
||||
#define IPQESS_REG_TXQ_CTRL 0x404
|
||||
#define IPQESS_TXQ_CTRL_IP_OPTION_EN 0x10
|
||||
#define IPQESS_TXQ_CTRL_TXQ_EN 0x20
|
||||
#define IPQESS_TXQ_CTRL_ENH_MODE 0x40
|
||||
#define IPQESS_TXQ_CTRL_LS_8023_EN 0x80
|
||||
#define IPQESS_TXQ_CTRL_TPD_BURST_EN 0x100
|
||||
#define IPQESS_TXQ_CTRL_LSO_BREAK_EN 0x200
|
||||
#define IPQESS_TXQ_NUM_TPD_BURST_MASK 0xF
|
||||
#define IPQESS_TXQ_TXF_BURST_NUM_MASK 0xFFFF
|
||||
#define IPQESS_TXQ_NUM_TPD_BURST_SHIFT 0
|
||||
#define IPQESS_TXQ_TXF_BURST_NUM_SHIFT 16
|
||||
|
||||
#define IPQESS_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
|
||||
#define IPQESS_TXF_WATER_MARK_MASK 0x0FFF
|
||||
#define IPQESS_TXF_LOW_WATER_MARK_SHIFT 0
|
||||
#define IPQESS_TXF_HIGH_WATER_MARK_SHIFT 16
|
||||
#define IPQESS_TXQ_CTRL_BURST_MODE_EN 0x80000000
|
||||
|
||||
/* WRR Control Register */
|
||||
#define IPQESS_REG_WRR_CTRL_Q0_Q3 0x40c
|
||||
#define IPQESS_REG_WRR_CTRL_Q4_Q7 0x410
|
||||
#define IPQESS_REG_WRR_CTRL_Q8_Q11 0x414
|
||||
#define IPQESS_REG_WRR_CTRL_Q12_Q15 0x418
|
||||
|
||||
/* Weight round robin(WRR), it takes queue as input, and computes
|
||||
* starting bits where we need to write the weight for a particular
|
||||
* queue
|
||||
*/
|
||||
#define IPQESS_WRR_SHIFT(x) (((x) * 5) % 20)
|
||||
|
||||
/* Tx Descriptor Control Register */
|
||||
#define IPQESS_REG_TPD_RING_SIZE 0x41C
|
||||
#define IPQESS_TPD_RING_SIZE_SHIFT 0
|
||||
#define IPQESS_TPD_RING_SIZE_MASK 0xFFFF
|
||||
|
||||
/* Transmit descriptor base address */
|
||||
#define IPQESS_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* TPD Index Register */
|
||||
#define IPQESS_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
#define IPQESS_TPD_PROD_IDX_BITS 0x0000FFFF
|
||||
#define IPQESS_TPD_CONS_IDX_BITS 0xFFFF0000
|
||||
#define IPQESS_TPD_PROD_IDX_MASK 0xFFFF
|
||||
#define IPQESS_TPD_CONS_IDX_MASK 0xFFFF
|
||||
#define IPQESS_TPD_PROD_IDX_SHIFT 0
|
||||
#define IPQESS_TPD_CONS_IDX_SHIFT 16
|
||||
|
||||
/* TX Virtual Queue Mapping Control Register */
|
||||
#define IPQESS_REG_VQ_CTRL0 0x4A0
|
||||
#define IPQESS_REG_VQ_CTRL1 0x4A4
|
||||
|
||||
/* Virtual QID shift, it takes queue as input, and computes
|
||||
* Virtual QID position in virtual qid control register
|
||||
*/
|
||||
#define IPQESS_VQ_ID_SHIFT(i) (((i) * 3) % 24)
|
||||
|
||||
/* Virtual Queue Default Value */
|
||||
#define IPQESS_VQ_REG_VALUE 0x240240
|
||||
|
||||
/* Tx side Port Interface Control Register */
|
||||
#define IPQESS_REG_PORT_CTRL 0x4A8
|
||||
#define IPQESS_PAD_EN_SHIFT 15
|
||||
|
||||
/* Tx side VLAN Configuration Register */
|
||||
#define IPQESS_REG_VLAN_CFG 0x4AC
|
||||
|
||||
#define IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT 0
|
||||
#define IPQESS_VLAN_CFG_SVLAN_TPID_MASK 0xffff
|
||||
#define IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT 16
|
||||
#define IPQESS_VLAN_CFG_CVLAN_TPID_MASK 0xffff
|
||||
|
||||
#define IPQESS_TX_CVLAN 16
|
||||
#define IPQESS_TX_INS_CVLAN 17
|
||||
#define IPQESS_TX_CVLAN_TAG_SHIFT 0
|
||||
|
||||
#define IPQESS_TX_SVLAN 14
|
||||
#define IPQESS_TX_INS_SVLAN 15
|
||||
#define IPQESS_TX_SVLAN_TAG_SHIFT 16
|
||||
|
||||
/* Tx Queue Packet Statistic Register */
|
||||
#define IPQESS_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
|
||||
|
||||
#define IPQESS_TX_STAT_PKT_MASK 0xFFFFFF
|
||||
|
||||
/* Tx Queue Byte Statistic Register */
|
||||
#define IPQESS_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
|
||||
|
||||
/* Load Balance Based Ring Offset Register */
|
||||
#define IPQESS_REG_LB_RING 0x800
|
||||
#define IPQESS_LB_RING_ENTRY_MASK 0xff
|
||||
#define IPQESS_LB_RING_ID_MASK 0x7
|
||||
#define IPQESS_LB_RING_PROFILE_ID_MASK 0x3
|
||||
#define IPQESS_LB_RING_ENTRY_BIT_OFFSET 8
|
||||
#define IPQESS_LB_RING_ID_OFFSET 0
|
||||
#define IPQESS_LB_RING_PROFILE_ID_OFFSET 3
|
||||
#define IPQESS_LB_REG_VALUE 0x6040200
|
||||
|
||||
/* Load Balance Priority Mapping Register */
|
||||
#define IPQESS_REG_LB_PRI_START 0x804
|
||||
#define IPQESS_REG_LB_PRI_END 0x810
|
||||
#define IPQESS_LB_PRI_REG_INC 4
|
||||
#define IPQESS_LB_PRI_ENTRY_BIT_OFFSET 4
|
||||
#define IPQESS_LB_PRI_ENTRY_MASK 0xf
|
||||
|
||||
/* RSS Priority Mapping Register */
|
||||
#define IPQESS_REG_RSS_PRI 0x820
|
||||
#define IPQESS_RSS_PRI_ENTRY_MASK 0xf
|
||||
#define IPQESS_RSS_RING_ID_MASK 0x7
|
||||
#define IPQESS_RSS_PRI_ENTRY_BIT_OFFSET 4
|
||||
|
||||
/* RSS Indirection Register */
|
||||
#define IPQESS_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
|
||||
#define IPQESS_NUM_IDT 16
|
||||
#define IPQESS_RSS_IDT_VALUE 0x64206420
|
||||
|
||||
/* Default RSS Ring Register */
|
||||
#define IPQESS_REG_DEF_RSS 0x890
|
||||
#define IPQESS_DEF_RSS_MASK 0x7
|
||||
|
||||
/* RSS Hash Function Type Register */
|
||||
#define IPQESS_REG_RSS_TYPE 0x894
|
||||
#define IPQESS_RSS_TYPE_NONE 0x01
|
||||
#define IPQESS_RSS_TYPE_IPV4TCP 0x02
|
||||
#define IPQESS_RSS_TYPE_IPV6_TCP 0x04
|
||||
#define IPQESS_RSS_TYPE_IPV4_UDP 0x08
|
||||
#define IPQESS_RSS_TYPE_IPV6UDP 0x10
|
||||
#define IPQESS_RSS_TYPE_IPV4 0x20
|
||||
#define IPQESS_RSS_TYPE_IPV6 0x40
|
||||
#define IPQESS_RSS_HASH_MODE_MASK 0x7f
|
||||
|
||||
#define IPQESS_REG_RSS_HASH_VALUE 0x8C0
|
||||
|
||||
#define IPQESS_REG_RSS_TYPE_RESULT 0x8C4
|
||||
|
||||
#define IPQESS_HASH_TYPE_START 0
|
||||
#define IPQESS_HASH_TYPE_END 5
|
||||
#define IPQESS_HASH_TYPE_SHIFT 12
|
||||
|
||||
#define IPQESS_RFS_FLOW_ENTRIES 1024
|
||||
#define IPQESS_RFS_FLOW_ENTRIES_MASK (IPQESS_RFS_FLOW_ENTRIES - 1)
|
||||
#define IPQESS_RFS_EXPIRE_COUNT_PER_CALL 128
|
||||
|
||||
/* RFD Base Address Register */
|
||||
#define IPQESS_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* RFD Index Register */
|
||||
#define IPQESS_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
#define IPQESS_RFD_PROD_IDX_BITS 0x00000FFF
|
||||
#define IPQESS_RFD_CONS_IDX_BITS 0x0FFF0000
|
||||
#define IPQESS_RFD_PROD_IDX_MASK 0xFFF
|
||||
#define IPQESS_RFD_CONS_IDX_MASK 0xFFF
|
||||
#define IPQESS_RFD_PROD_IDX_SHIFT 0
|
||||
#define IPQESS_RFD_CONS_IDX_SHIFT 16
|
||||
|
||||
/* Rx Descriptor Control Register */
|
||||
#define IPQESS_REG_RX_DESC0 0xA10
|
||||
#define IPQESS_RFD_RING_SIZE_MASK 0xFFF
|
||||
#define IPQESS_RX_BUF_SIZE_MASK 0xFFFF
|
||||
#define IPQESS_RFD_RING_SIZE_SHIFT 0
|
||||
#define IPQESS_RX_BUF_SIZE_SHIFT 16
|
||||
|
||||
#define IPQESS_REG_RX_DESC1 0xA14
|
||||
#define IPQESS_RXQ_RFD_BURST_NUM_MASK 0x3F
|
||||
#define IPQESS_RXQ_RFD_PF_THRESH_MASK 0x1F
|
||||
#define IPQESS_RXQ_RFD_LOW_THRESH_MASK 0xFFF
|
||||
#define IPQESS_RXQ_RFD_BURST_NUM_SHIFT 0
|
||||
#define IPQESS_RXQ_RFD_PF_THRESH_SHIFT 8
|
||||
#define IPQESS_RXQ_RFD_LOW_THRESH_SHIFT 16
|
||||
|
||||
/* RXQ Control Register */
|
||||
#define IPQESS_REG_RXQ_CTRL 0xA18
|
||||
#define IPQESS_FIFO_THRESH_TYPE_SHIF 0
|
||||
#define IPQESS_FIFO_THRESH_128_BYTE 0x0
|
||||
#define IPQESS_FIFO_THRESH_64_BYTE 0x1
|
||||
#define IPQESS_RXQ_CTRL_RMV_VLAN 0x00000002
|
||||
#define IPQESS_RXQ_CTRL_EN_MASK GENMASK(15, 8)
|
||||
#define IPQESS_RXQ_CTRL_EN(__qid) BIT(8 + (__qid))
|
||||
|
||||
/* AXI Burst Size Config */
|
||||
#define IPQESS_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
|
||||
#define IPQESS_AXIW_MAXWRSIZE_VALUE 0x0
|
||||
|
||||
/* Rx Statistics Register */
|
||||
#define IPQESS_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
|
||||
#define IPQESS_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* WoL Pattern Length Register */
|
||||
#define IPQESS_REG_WOL_PATTERN_LEN0 0xC00
|
||||
#define IPQESS_WOL_PT_LEN_MASK 0xFF
|
||||
#define IPQESS_WOL_PT0_LEN_SHIFT 0
|
||||
#define IPQESS_WOL_PT1_LEN_SHIFT 8
|
||||
#define IPQESS_WOL_PT2_LEN_SHIFT 16
|
||||
#define IPQESS_WOL_PT3_LEN_SHIFT 24
|
||||
|
||||
#define IPQESS_REG_WOL_PATTERN_LEN1 0xC04
|
||||
#define IPQESS_WOL_PT4_LEN_SHIFT 0
|
||||
#define IPQESS_WOL_PT5_LEN_SHIFT 8
|
||||
#define IPQESS_WOL_PT6_LEN_SHIFT 16
|
||||
|
||||
/* WoL Control Register */
|
||||
#define IPQESS_REG_WOL_CTRL 0xC08
|
||||
#define IPQESS_WOL_WK_EN 0x00000001
|
||||
#define IPQESS_WOL_MG_EN 0x00000002
|
||||
#define IPQESS_WOL_PT0_EN 0x00000004
|
||||
#define IPQESS_WOL_PT1_EN 0x00000008
|
||||
#define IPQESS_WOL_PT2_EN 0x00000010
|
||||
#define IPQESS_WOL_PT3_EN 0x00000020
|
||||
#define IPQESS_WOL_PT4_EN 0x00000040
|
||||
#define IPQESS_WOL_PT5_EN 0x00000080
|
||||
#define IPQESS_WOL_PT6_EN 0x00000100
|
||||
|
||||
/* MAC Control Register */
|
||||
#define IPQESS_REG_MAC_CTRL0 0xC20
|
||||
#define IPQESS_REG_MAC_CTRL1 0xC24
|
||||
|
||||
/* WoL Pattern Register */
|
||||
#define IPQESS_REG_WOL_PATTERN_START 0x5000
|
||||
#define IPQESS_PATTERN_PART_REG_OFFSET 0x40
|
||||
|
||||
|
||||
/* TX descriptor fields */
|
||||
#define IPQESS_TPD_HDR_SHIFT 0
|
||||
#define IPQESS_TPD_PPPOE_EN 0x00000100
|
||||
#define IPQESS_TPD_IP_CSUM_EN 0x00000200
|
||||
#define IPQESS_TPD_TCP_CSUM_EN 0x0000400
|
||||
#define IPQESS_TPD_UDP_CSUM_EN 0x00000800
|
||||
#define IPQESS_TPD_CUSTOM_CSUM_EN 0x00000C00
|
||||
#define IPQESS_TPD_LSO_EN 0x00001000
|
||||
#define IPQESS_TPD_LSO_V2_EN 0x00002000
|
||||
/* The VLAN_TAGGED bit is not used in the publicly available
|
||||
* drivers. The definition has been stolen from the Atheros
|
||||
* 'alx' driver (drivers/net/ethernet/atheros/alx/hw.h). It
|
||||
* seems that it has the same meaning in regard to the EDMA
|
||||
* hardware.
|
||||
*/
|
||||
#define IPQESS_TPD_VLAN_TAGGED 0x00004000
|
||||
#define IPQESS_TPD_IPV4_EN 0x00010000
|
||||
#define IPQESS_TPD_MSS_MASK 0x1FFF
|
||||
#define IPQESS_TPD_MSS_SHIFT 18
|
||||
#define IPQESS_TPD_CUSTOM_CSUM_SHIFT 18
|
||||
|
||||
/* RRD descriptor fields */
|
||||
#define IPQESS_RRD_NUM_RFD_MASK 0x000F
|
||||
#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
|
||||
#define IPQESS_RRD_SRC_PORT_NUM_MASK 0x4000
|
||||
#define IPQESS_RRD_SVLAN 0x8000
|
||||
#define IPQESS_RRD_FLOW_COOKIE_MASK 0x07FF;
|
||||
|
||||
#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
|
||||
#define IPQESS_RRD_CSUM_FAIL_MASK 0xC000
|
||||
#define IPQESS_RRD_CVLAN 0x0001
|
||||
#define IPQESS_RRD_DESC_VALID 0x8000
|
||||
|
||||
#define IPQESS_RRD_PRIORITY_SHIFT 4
|
||||
#define IPQESS_RRD_PRIORITY_MASK 0x7
|
||||
#define IPQESS_RRD_PORT_TYPE_SHIFT 7
|
||||
#define IPQESS_RRD_PORT_TYPE_MASK 0x1F
|
||||
|
||||
#endif
|
||||
@@ -1,175 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR ISC)
|
||||
/* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all copies.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/phylink.h>
|
||||
|
||||
#include "ipqess.h"
|
||||
|
||||
struct ipqesstool_stats {
|
||||
uint8_t string[ETH_GSTRING_LEN];
|
||||
uint32_t offset;
|
||||
};
|
||||
|
||||
#define IPQESS_STAT(m) offsetof(struct ipqesstool_statistics, m)
|
||||
#define DRVINFO_LEN 32
|
||||
|
||||
static const struct ipqesstool_stats ipqess_stats[] = {
|
||||
{"tx_q0_pkt", IPQESS_STAT(tx_q0_pkt)},
|
||||
{"tx_q1_pkt", IPQESS_STAT(tx_q1_pkt)},
|
||||
{"tx_q2_pkt", IPQESS_STAT(tx_q2_pkt)},
|
||||
{"tx_q3_pkt", IPQESS_STAT(tx_q3_pkt)},
|
||||
{"tx_q4_pkt", IPQESS_STAT(tx_q4_pkt)},
|
||||
{"tx_q5_pkt", IPQESS_STAT(tx_q5_pkt)},
|
||||
{"tx_q6_pkt", IPQESS_STAT(tx_q6_pkt)},
|
||||
{"tx_q7_pkt", IPQESS_STAT(tx_q7_pkt)},
|
||||
{"tx_q8_pkt", IPQESS_STAT(tx_q8_pkt)},
|
||||
{"tx_q9_pkt", IPQESS_STAT(tx_q9_pkt)},
|
||||
{"tx_q10_pkt", IPQESS_STAT(tx_q10_pkt)},
|
||||
{"tx_q11_pkt", IPQESS_STAT(tx_q11_pkt)},
|
||||
{"tx_q12_pkt", IPQESS_STAT(tx_q12_pkt)},
|
||||
{"tx_q13_pkt", IPQESS_STAT(tx_q13_pkt)},
|
||||
{"tx_q14_pkt", IPQESS_STAT(tx_q14_pkt)},
|
||||
{"tx_q15_pkt", IPQESS_STAT(tx_q15_pkt)},
|
||||
{"tx_q0_byte", IPQESS_STAT(tx_q0_byte)},
|
||||
{"tx_q1_byte", IPQESS_STAT(tx_q1_byte)},
|
||||
{"tx_q2_byte", IPQESS_STAT(tx_q2_byte)},
|
||||
{"tx_q3_byte", IPQESS_STAT(tx_q3_byte)},
|
||||
{"tx_q4_byte", IPQESS_STAT(tx_q4_byte)},
|
||||
{"tx_q5_byte", IPQESS_STAT(tx_q5_byte)},
|
||||
{"tx_q6_byte", IPQESS_STAT(tx_q6_byte)},
|
||||
{"tx_q7_byte", IPQESS_STAT(tx_q7_byte)},
|
||||
{"tx_q8_byte", IPQESS_STAT(tx_q8_byte)},
|
||||
{"tx_q9_byte", IPQESS_STAT(tx_q9_byte)},
|
||||
{"tx_q10_byte", IPQESS_STAT(tx_q10_byte)},
|
||||
{"tx_q11_byte", IPQESS_STAT(tx_q11_byte)},
|
||||
{"tx_q12_byte", IPQESS_STAT(tx_q12_byte)},
|
||||
{"tx_q13_byte", IPQESS_STAT(tx_q13_byte)},
|
||||
{"tx_q14_byte", IPQESS_STAT(tx_q14_byte)},
|
||||
{"tx_q15_byte", IPQESS_STAT(tx_q15_byte)},
|
||||
{"rx_q0_pkt", IPQESS_STAT(rx_q0_pkt)},
|
||||
{"rx_q1_pkt", IPQESS_STAT(rx_q1_pkt)},
|
||||
{"rx_q2_pkt", IPQESS_STAT(rx_q2_pkt)},
|
||||
{"rx_q3_pkt", IPQESS_STAT(rx_q3_pkt)},
|
||||
{"rx_q4_pkt", IPQESS_STAT(rx_q4_pkt)},
|
||||
{"rx_q5_pkt", IPQESS_STAT(rx_q5_pkt)},
|
||||
{"rx_q6_pkt", IPQESS_STAT(rx_q6_pkt)},
|
||||
{"rx_q7_pkt", IPQESS_STAT(rx_q7_pkt)},
|
||||
{"rx_q0_byte", IPQESS_STAT(rx_q0_byte)},
|
||||
{"rx_q1_byte", IPQESS_STAT(rx_q1_byte)},
|
||||
{"rx_q2_byte", IPQESS_STAT(rx_q2_byte)},
|
||||
{"rx_q3_byte", IPQESS_STAT(rx_q3_byte)},
|
||||
{"rx_q4_byte", IPQESS_STAT(rx_q4_byte)},
|
||||
{"rx_q5_byte", IPQESS_STAT(rx_q5_byte)},
|
||||
{"rx_q6_byte", IPQESS_STAT(rx_q6_byte)},
|
||||
{"rx_q7_byte", IPQESS_STAT(rx_q7_byte)},
|
||||
{"tx_desc_error", IPQESS_STAT(tx_desc_error)},
|
||||
};
|
||||
|
||||
static int ipqess_get_strset_count(struct net_device *netdev, int sset)
|
||||
{
|
||||
switch (sset) {
|
||||
case ETH_SS_STATS:
|
||||
return ARRAY_SIZE(ipqess_stats);
|
||||
default:
|
||||
netdev_dbg(netdev, "%s: Invalid string set", __func__);
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
static void ipqess_get_strings(struct net_device *netdev, uint32_t stringset,
|
||||
uint8_t *data)
|
||||
{
|
||||
uint8_t *p = data;
|
||||
uint32_t i;
|
||||
|
||||
switch (stringset) {
|
||||
case ETH_SS_STATS:
|
||||
for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++) {
|
||||
memcpy(p, ipqess_stats[i].string,
|
||||
min((size_t)ETH_GSTRING_LEN,
|
||||
strlen(ipqess_stats[i].string) + 1));
|
||||
p += ETH_GSTRING_LEN;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void ipqess_get_ethtool_stats(struct net_device *netdev,
|
||||
struct ethtool_stats *stats,
|
||||
uint64_t *data)
|
||||
{
|
||||
struct ipqess *ess = netdev_priv(netdev);
|
||||
u32 *essstats = (u32 *)&ess->ipqessstats;
|
||||
int i;
|
||||
|
||||
spin_lock(&ess->stats_lock);
|
||||
|
||||
ipqess_update_hw_stats(ess);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++)
|
||||
data[i] = *(u32 *)(essstats + (ipqess_stats[i].offset / sizeof(u32)));
|
||||
|
||||
spin_unlock(&ess->stats_lock);
|
||||
}
|
||||
|
||||
static void ipqess_get_drvinfo(struct net_device *dev,
|
||||
struct ethtool_drvinfo *info)
|
||||
{
|
||||
strlcpy(info->driver, "qca_ipqess", DRVINFO_LEN);
|
||||
strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
|
||||
}
|
||||
|
||||
static int ipqess_get_settings(struct net_device *netdev,
|
||||
struct ethtool_link_ksettings *cmd)
|
||||
{
|
||||
struct ipqess *ess = netdev_priv(netdev);
|
||||
|
||||
return phylink_ethtool_ksettings_get(ess->phylink, cmd);
|
||||
}
|
||||
|
||||
static int ipqess_set_settings(struct net_device *netdev,
|
||||
const struct ethtool_link_ksettings *cmd)
|
||||
{
|
||||
struct ipqess *ess = netdev_priv(netdev);
|
||||
|
||||
return phylink_ethtool_ksettings_set(ess->phylink, cmd);
|
||||
}
|
||||
|
||||
static void ipqess_get_ringparam(struct net_device *netdev,
|
||||
struct ethtool_ringparam *ring)
|
||||
{
|
||||
ring->tx_max_pending = IPQESS_TX_RING_SIZE;
|
||||
ring->rx_max_pending = IPQESS_RX_RING_SIZE;
|
||||
}
|
||||
|
||||
static const struct ethtool_ops ipqesstool_ops = {
|
||||
.get_drvinfo = &ipqess_get_drvinfo,
|
||||
.get_link = ðtool_op_get_link,
|
||||
.get_link_ksettings = &ipqess_get_settings,
|
||||
.set_link_ksettings = &ipqess_set_settings,
|
||||
.get_strings = &ipqess_get_strings,
|
||||
.get_sset_count = &ipqess_get_strset_count,
|
||||
.get_ethtool_stats = &ipqess_get_ethtool_stats,
|
||||
.get_ringparam = ipqess_get_ringparam,
|
||||
};
|
||||
|
||||
void ipqess_set_ethtool_ops(struct net_device *netdev)
|
||||
{
|
||||
netdev->ethtool_ops = &ipqesstool_ops;
|
||||
}
|
||||
Reference in New Issue
Block a user