forked from Ivasoft/openwrt
oxnas: move PCIe controller outside of simple-bus
Move PCIe controller outside down to SoC level to avoid resource mapping problems. Also add more detailed error handling when mapping registers. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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@@ -420,34 +420,51 @@ oxnas_pcie_map_registers(struct platform_device *pdev,
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u32 pcie_ctrl_offset;
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ret = of_address_to_resource(np, 0, ®s);
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if (ret)
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if (ret) {
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dev_err(&pdev->dev, "failed to parse base register space\n");
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return -EINVAL;
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}
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pcie->base = devm_ioremap_resource(&pdev->dev, ®s);
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if (!pcie->base)
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if (!pcie->base) {
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dev_err(&pdev->dev, "failed to map base register space\n");
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return -ENOMEM;
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}
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ret = of_address_to_resource(np, 1, ®s);
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if (ret)
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if (ret) {
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dev_err(&pdev->dev, "failed to parse inbound register space\n");
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return -EINVAL;
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}
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pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s);
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if (!pcie->inbound)
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if (!pcie->inbound) {
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dev_err(&pdev->dev, "failed to map inbound register space\n");
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return -ENOMEM;
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}
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pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL);
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if (IS_ERR(pcie->phy)) {
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if (PTR_ERR(pcie->phy) == -EPROBE_DEFER)
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if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) {
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dev_err(&pdev->dev, "failed to probe phy\n");
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return PTR_ERR(pcie->phy);
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}
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dev_warn(&pdev->dev, "phy not attached\n");
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pcie->phy = NULL;
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}
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if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
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&outbound_ctrl_offset))
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&outbound_ctrl_offset)) {
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dev_err(&pdev->dev, "failed to parse outbound register offset\n");
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return -EINVAL;
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}
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pcie->outbound_offset = outbound_ctrl_offset;
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if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
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&pcie_ctrl_offset))
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&pcie_ctrl_offset)) {
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dev_err(&pdev->dev, "failed to parse pcie-ctrl register offset\n");
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return -EINVAL;
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}
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pcie->pcie_ctrl_offset = pcie_ctrl_offset;
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return 0;
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