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ipq806x: 5.15: replace dtsi patches with upstream version

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Reorganize dtsi patches with upstream version and drop dtsi in 5.15
files.
Also add an additional upstream patch for hwspinlock support.
Refresh all the dts with needed changes.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi
2022-06-16 22:12:01 +02:00
parent bd02eb7502
commit 88bf652525
48 changed files with 1618 additions and 1179 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8062.dtsi"
#include "qcom-ipq8062-smb208.dtsi"
#include <dt-bindings/input/input.h>
/delete-node/ &nand_pins;
@@ -134,6 +134,15 @@
};
};
/* nand_pins are used for leds_pins, empty the node
* from ipq8064.dtsi
*/
&nand_pins {
/delete-property/ disable;
/delete-property/ pullups;
/delete-property/ hold;
};
&qcom_pinmux {
pinctrl-0 = <&akro_pins>;
pinctrl-names = "default";

98
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062.dtsi
View File

@@ -1,98 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "qcom-ipq8064.dtsi"
/ {
model = "Qualcomm IPQ8062";
compatible = "qcom,ipq8062", "qcom,ipq8064";
aliases {
serial0 = &gsbi4_serial;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
};
&gsbi4 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
serial@16340000 {
status = "okay";
};
/*
* The i2c device on gsbi4 should not be enabled.
* On ipq806x designs gsbi4 i2c is meant for exclusive
* RPM usage. Turning this on in kernel manifests as
* i2c failure for the RPM.
*/
};
&opp_table0 {
/delete-node/opp-1200000000;
/delete-node/opp-1400000000;
/*
* Voltage thresholds are <target min max>
*/
opp-384000000 {
opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>;
opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>;
opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>;
};
opp-600000000 {
opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;
opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>;
opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>;
};
opp-800000000 {
opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>;
opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>;
};
opp-1000000000 {
opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>;
};
};
&pcie0 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie1 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie2 {
compatible = "qcom,pcie-ipq8064-v2";
};
&smb208_s2a {
regulator-max-microvolt = <1150000>;
};
&smb208_s2b {
regulator-max-microvolt = <1150000>;
};

2
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>

3
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
View File

@@ -54,9 +54,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
View File

@@ -25,7 +25,7 @@
};
&qcom_pinmux {
rgmii2_pins: rgmii2_pins {
rgmii2_pins: rgmii2-pins {
mux {
pins = "gpio27", "gpio28", "gpio29",
"gpio30", "gpio31", "gpio32",
@@ -66,9 +66,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

8
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
View File

@@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
@@ -234,12 +234,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
@@ -37,9 +37,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

81
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
@@ -158,26 +158,77 @@
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x000e4 0x6a545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
>;
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
qca8k,rgmii56_1_8v;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "lan4";
};
port@5 {
reg = <5>;
label = "wan";
};
/*
port@6 {
reg = <0>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
asym-pause;
};
};
*/
};
};
};
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

3
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
View File

@@ -167,9 +167,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
View File

@@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
@@ -231,9 +231,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

4
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -221,8 +221,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
};

69
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
View File

@@ -1,69 +0,0 @@
#include "qcom-ipq8064.dtsi"
/ {
aliases {
serial0 = &gsbi4_serial;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
};
&gsbi4 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
serial@16340000 {
status = "okay";
};
/*
* The i2c device on gsbi4 should not be enabled.
* On ipq806x designs gsbi4 i2c is meant for exclusive
* RPM usage. Turning this on in kernel manifests as
* i2c failure for the RPM.
*/
};
&CPU_SPC {
status = "okay";
};
&pcie0 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie1 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie2 {
compatible = "qcom,pcie-ipq8064-v2";
};
&sata {
ports-implemented = <0x1>;
};
&ss_phy_0 {
qcom,rx-eq = <2>;
qcom,tx-deamp_3_5db = <32>;
qcom,mpll = <5>;
};
&ss_phy_1 {
qcom,rx-eq = <2>;
qcom,tx-deamp_3_5db = <32>;
qcom,mpll = <5>;
};

2
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
View File

@@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>

2
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
View File

@@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
@@ -159,9 +159,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
cs@0 {
reg = <0>;
compatible = "qcom,nandcs";

6
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
View File

@@ -1,4 +1,4 @@
#include "qcom-ipq8065.dtsi"
#include "qcom-ipq8065-smb208.dtsi"
#include <dt-bindings/input/input.h>
@@ -108,14 +108,14 @@
};
};
mdio0_pins: mdio0_pins {
mdio0_pins: mdio0-pins {
clk {
pins = "gpio1";
input-disable;
};
};
rgmii2_pins: rgmii2_pins {
rgmii2_pins: rgmii2-pins {
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
input-disable;

9
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi
View File

@@ -1,4 +1,4 @@
#include "qcom-ipq8065.dtsi"
#include "qcom-ipq8065-smb208.dtsi"
#include <dt-bindings/input/input.h>
@@ -124,14 +124,14 @@
};
};
mdio0_pins: mdio0_pins {
mdio0_pins: mdio0-pins {
clk {
pins = "gpio1";
input-disable;
};
};
rgmii2_pins: rgmii2_pins {
rgmii2_pins: rgmii2-pins {
tx {
pins = "gpio27", "gpio28", "gpio29",
"gpio30", "gpio31", "gpio32";
@@ -223,9 +223,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

7
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq8065.dtsi"
#include "qcom-ipq8065-smb208.dtsi"
#include <dt-bindings/input/input.h>
/ {
@@ -82,7 +82,7 @@
};
};
rgmii2_pins: rgmii2_pins {
rgmii2_pins: rgmii2-pins {
mux {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
@@ -130,9 +130,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

7
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq8065.dtsi"
#include "qcom-ipq8065-smb208.dtsi"
#include <dt-bindings/input/input.h>
/ {
@@ -81,7 +81,7 @@
};
};
rgmii2_pins: rgmii2_pins {
rgmii2_pins: rgmii2-pins {
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
input-disable;
@@ -119,9 +119,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";

167
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065.dtsi
View File

@@ -1,167 +0,0 @@
#include "qcom-ipq8064.dtsi"
/ {
model = "Qualcomm IPQ8065";
compatible = "qcom,ipq8065", "qcom,ipq8064";
aliases {
serial0 = &gsbi4_serial;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
};
&gsbi4 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
serial@16340000 {
status = "okay";
};
/*
* The i2c device on gsbi4 should not be enabled.
* On ipq806x designs gsbi4 i2c is meant for exclusive
* RPM usage. Turning this on in kernel manifests as
* i2c failure for the RPM.
*/
};
&pcie0 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie1 {
compatible = "qcom,pcie-ipq8064-v2";
};
&pcie2 {
compatible = "qcom,pcie-ipq8064-v2";
};
&sata {
ports-implemented = <0x1>;
};
&smb208_s2a {
regulator-min-microvolt = <775000>;
regulator-max-microvolt = <1275000>;
};
&smb208_s2b {
regulator-min-microvolt = <775000>;
regulator-max-microvolt = <1275000>;
};
&ss_phy_0 {
qcom,rx-eq = <2>;
qcom,tx-deamp_3_5db = <32>;
qcom,mpll = <5>;
};
&ss_phy_1 {
qcom,rx-eq = <2>;
qcom,tx-deamp_3_5db = <32>;
qcom,mpll = <5>;
};
&opp_table_l2 {
/delete-node/opp-1200000000;
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1150000>;
clock-latency-ns = <100000>;
opp-level = <2>;
};
};
&opp_table0 {
/*
* On ipq8065 1.2 ghz freq is not present
* Remove it to make cpufreq work and not
* complain for missing definition
*/
/delete-node/opp-1200000000;
/*
* Voltage thresholds are <target min max>
*/
opp-384000000 {
opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
};
opp-600000000 {
opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
};
opp-800000000 {
opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
};
opp-1000000000 {
opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
};
opp-1400000000 {
opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
opp-level = <1>;
};
opp-1725000000 {
opp-hz = /bits/ 64 <1725000000>;
opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
opp-supported-hw = <0x1>;
clock-latency-ns = <100000>;
opp-level = <2>;
};
};

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
/ {
memory {
@@ -140,9 +140,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
compatible = "qcom,nandcs";

5
target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
View File

@@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
@@ -262,9 +262,6 @@
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
compatible = "qcom,nandcs";