forked from Ivasoft/openwrt
cleanup uboot package
SVN-Revision: 13291
This commit is contained in:
Thomas Langer
@@ -28,8 +28,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/ifx_cfg.h>
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#define USE_REFERENCE_BOARD
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//#define USE_EVALUATION_BOARD
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@@ -45,8 +43,12 @@
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//#define DANUBE_DDR_RAM_133M
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#define DANUBE_DDR_RAM_SIZE 32 /* 32M DDR-DRAM for reference board */
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#endif
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#define CONFIG_LZMA 1 /* use LZMA for compression */
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#define CLK_OUT2_25MHZ
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#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
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#define CONFIG_IFX_MIPS 1 /* in an Infineon chip */
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#define CONFIG_DANUBE 1 /* on a danube Board */
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#define RAM_SIZE 0x2000000 /*32M ram*/
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@@ -63,7 +65,7 @@
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 300, 9600, 19200, 38400, 57600, 115200 }
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#ifndef CFG_HEAD_CODE
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#ifndef CFG_BOOTSTRAP_CODE
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#endif
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@@ -78,15 +80,24 @@
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"ethaddr=11:22:33:44:55:66\0" \
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"serverip=192.168.45.100\0" \
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"ipaddr=192.168.45.108\0" \
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"ram_addr=0x80500000\0" \
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"kernel_addr=0xb0030000\0" \
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"flashargs=setenv bootargs rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} init=/etc/preinit\0" \
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"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
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"addmisc=setenv bootargs ${bootargs} console=ttyS1,115200 ethaddr=${ethaddr} ${mtdparts}\0" \
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"flash_flash=run flashargs addip addmisc;bootm ${kernel_addr}\0" \
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"flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \
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"net_flash=run load_kernel flashargs addip addmisc;bootm ${ram_addr}\0" \
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"net_nfs=run load_kernel nfsargs addip addmisc;bootm ${ram_addr}\0" \
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"load_kernel=tftp ${ram_addr} ${tftppath}openwrt-ifxmips-uImage\0" \
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"update_uboot=tftp 0x80500000 u-boot.ifx;era 1:0-10; cp.b 0x80500000 0xb0000000 0x10000\0" \
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"update_openwrt=tftp 0x80500000 openwrt-ifxmips-squashfs.image; era 1:10-120; cp.b 0x80500000 0xb0030000 0x300000\0" \
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"bootargs=console=ttyS1,115200 rootfstype=squashfs,jffs2 init=/etc/preinit\0"
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"update_openwrt=tftp ${ram_addr} ${tftppath}openwrt-ifxmips-squashfs.image; era ${kernel_addr} +${filesize} 0; cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
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#define CONFIG_BOOTCOMMAND "bootm 0xb0030000"
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#define CONFIG_BOOTCOMMAND "run flash_flash"
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#define CONFIG_COMMANDS_YES (CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DHRYSTONE | \
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CFG_CMD_NET )
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#define CONFIG_COMMANDS_NO (CFG_CMD_NFS | \
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@@ -159,8 +170,8 @@
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//#define CFG_ENV_IS_NOWHERE 1
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//#define CFG_ENV_IS_IN_NVRAM 1
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/* Address and size of Primary Environment Sector */
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#define CFG_ENV_ADDR IFX_CFG_FLASH_UBOOT_CFG_START_ADDR
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#define CFG_ENV_SIZE IFX_CFG_FLASH_UBOOT_CFG_SIZE
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#define CFG_ENV_ADDR 0xB0020000
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#define CFG_ENV_SIZE 0x10000
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#define CONFIG_FLASH_16BIT
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@@ -1,249 +0,0 @@
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/* ============================================================================
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* Copyright (C) 2003[- 2004] ? Infineon Technologies AG.
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*
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* All rights reserved.
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* ============================================================================
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*
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* ============================================================================
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*
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* This document contains proprietary information belonging to Infineon
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* Technologies AG. Passing on and copying of this document, and communication
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* of its contents is not permitted without prior written authorisation.
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*
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* ============================================================================
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*
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* File Name: ifx_cfg.h
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* Author : Mars Lin (mars.lin@infineon.com)
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* Date:
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*
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* ===========================================================================
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*
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* Project:
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* Block:
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*
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* ===========================================================================
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* Contents: This file contains the data structures and definitions used
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* by the core iptables and the sip alg modules.
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* ===========================================================================
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* References:
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*/
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/*
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* This file contains the configuration parameters for the IFX board.
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*/
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#ifndef _DANUBE_CFG_H_
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#define _DANUBE_CFG_H_
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/*-----------------------------------------------------------------------
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* U-Boot/Kernel configurations
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*/
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#define IFX_CFG_UBOOT_DEFAULT_CFG_IPADDR "172.20.80.100"
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#define IFX_CFG_UBOOT_DEFAULT_CFG_SERVERIP "172.20.80.2"
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#define IFX_CFG_UBOOT_DEFAULT_CFG_ETHADDR "00:E0:92:00:01:40"
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#define IFX_CFG_UBOOT_DEFAULT_CFG_NETDEV "eth1"
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#define IFX_CFG_UBOOT_DEFAULT_CFG_BAUDRATE "115200"
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#define IFX_CFG_UBOOT_LOAD_ADDRESS "0x80800000"
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/* End of U-Boot/Kernel configurations
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*-----------------------------------------------------------------------
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*/
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/*-----------------------------------------------------------------------
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* Board specific configurations
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*/
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#ifdef IFX_CONFIG_MEMORY_SIZE
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#define IFX_CFG_MEM_SIZE 31
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#else
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#error "ERROR!! Define memory size first!"
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#endif
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//2MB flash partition
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#if (IFX_CONFIG_FLASH_SIZE == 2)
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#define IFX_CFG_FLASH_PARTITIONS_INFO \
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"part0_begin=0xB0000000\0" \
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"part1_begin=0xB0010000\0" \
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"part2_begin=0xB0050000\0" \
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"total_part=3\0"
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#define IFX_CFG_FLASH_DATA_BLOCKS_INFO \
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"data_block0=" IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "\0" \
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"data_block1=" IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "\0" \
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"data_block2=" IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "\0" \
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"data_block3=" IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "\0" \
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"data_block4=" IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "\0" \
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"data_block5=" IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "\0" \
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"data_block6=" IFX_CFG_FLASH_FIRMWARE_DIAG_BLOCK_NAME "\0" \
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"data_block7=" IFX_CFG_FLASH_CALIBRATION_CFG_BLOCK_NAME "\0" \
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"total_db=8\0"
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#define IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "uboot"
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#define IFX_CFG_FLASH_UBOOT_IMAGE_START_ADDR 0xB0000000
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#define IFX_CFG_FLASH_UBOOT_IMAGE_SIZE 0
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#define IFX_CFG_FLASH_UBOOT_IMAGE_MTDBLOCK_NAME "/dev/mtdblock0"
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "firmware"
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_START_ADDR 0xB0010000
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_SIZE 0
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_MTDBLOCK_NAME "/dev/mtdblock1"
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "rootfs"
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_START_ADDR 0xB0050000
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_SIZE 0
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_MTDBLOCK_NAME "/dev/mtdblock2"
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#define IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "kernel"
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#define IFX_CFG_FLASH_KERNEL_IMAGE_START_ADDR 0xB01FCFFF
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#define IFX_CFG_FLASH_KERNEL_IMAGE_SIZE 0
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#define IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "sysconfig"
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#define IFX_CFG_FLASH_SYSTEM_CFG_START_ADDR 0xB01FD000
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#define IFX_CFG_FLASH_SYSTEM_CFG_SIZE 0
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#define IFX_CFG_FLASH_SYSTEM_CFG_END_ADDR 0xB01FEFFF
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#define IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "ubootconfig"
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#define IFX_CFG_FLASH_UBOOT_CFG_START_ADDR 0xB01FF000
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#define IFX_CFG_FLASH_UBOOT_CFG_SIZE 0x0C00
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#define IFX_CFG_FLASH_UBOOT_CFG_END_ADDR 0xB01FFBFF
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#define IFX_CFG_FLASH_FIRMWARE_DIAG_BLOCK_NAME "fwdiag"
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#define IFX_CFG_FLASH_FIRMWARE_DIAG_START_ADDR 0xB31FFC00
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#define IFX_CFG_FLASH_FIRMWARE_DIAG_SIZE 0x0200
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#define IFX_CFG_FLASH_FIRMWARE_DIAG_END_ADDR 0xB01FFDFF
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#define IFX_CFG_FLASH_CALIBRATION_CFG_BLOCK_NAME "calibration"
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#define IFX_CFG_FLASH_CALIBRATION_CFG_START_ADDR 0xB01FFE00
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#define IFX_CFG_FLASH_CALIBRATION_CFG_SIZE 0x0200
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#define IFX_CFG_FLASH_CALIBRATION_CFG_END_ADDR 0xB01FFFFF
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#define IFX_CFG_FLASH_END_ADDR 0xB01FFFFF
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//4MB flash partition
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#elif (IFX_CONFIG_FLASH_SIZE == 4)
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#define IFX_CFG_FLASH_PARTITIONS_INFO \
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"part0_begin=0xB0000000\0" \
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"part1_begin=0xB0020000\0" \
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"part2_begin=0xB0060000\0" \
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"total_part=3\0"
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#define IFX_CFG_FLASH_DATA_BLOCKS_INFO \
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"data_block0=" IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "\0" \
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"data_block1=" IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "\0" \
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"data_block2=" IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "\0" \
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"data_block3=" IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "\0" \
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"data_block4=" IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "\0" \
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"data_block5=" IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "\0" \
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"data_block6=" IFX_CFG_FLASH_VOIP_CFG_BLOCK_NAME "\0" \
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"data_block7=" IFX_CFG_FLASH_FIRMWARE_DIAG_BLOCK_NAME "\0" \
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"data_block8=" IFX_CFG_FLASH_CALIBRATION_CFG_BLOCK_NAME "\0" \
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"total_db=9\0"
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#define IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "uboot"
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#define IFX_CFG_FLASH_UBOOT_IMAGE_START_ADDR 0xB0000000
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#define IFX_CFG_FLASH_UBOOT_IMAGE_SIZE 0
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#define IFX_CFG_FLASH_UBOOT_IMAGE_MTDBLOCK_NAME "/dev/mtdblock0"
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "firmware"
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_START_ADDR 0xB0020000
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_SIZE 0
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_MTDBLOCK_NAME "/dev/mtdblock1"
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "rootfs"
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_START_ADDR 0xB0060000
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_SIZE 0
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_MTDBLOCK_NAME "/dev/mtdblock2"
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#define IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "kernel"
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#define IFX_CFG_FLASH_KERNEL_IMAGE_START_ADDR 0xB03F4FFF
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#define IFX_CFG_FLASH_KERNEL_IMAGE_SIZE 0
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#define IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "sysconfig"
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#define IFX_CFG_FLASH_SYSTEM_CFG_START_ADDR 0xB03F5000
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#define IFX_CFG_FLASH_SYSTEM_CFG_SIZE 0x2000
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#define IFX_CFG_FLASH_SYSTEM_CFG_END_ADDR 0xB03F6FFF
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#define IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "ubootconfig"
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#define IFX_CFG_FLASH_UBOOT_CFG_START_ADDR 0xB03F7000
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#define IFX_CFG_FLASH_UBOOT_CFG_SIZE 0x0C00
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#define IFX_CFG_FLASH_UBOOT_CFG_END_ADDR 0xB03F7BFF
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#define IFX_CFG_FLASH_VOIP_CFG_BLOCK_NAME "voip"
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#define IFX_CFG_FLASH_VOIP_CFG_START_ADDR 0xB03F7C00
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#define IFX_CFG_FLASH_VOIP_CFG_SIZE 0x8000
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#define IFX_CFG_FLASH_VOIP_CFG_END_ADDR 0xB03FFBFF
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#define IFX_CFG_FLASH_FIRMWARE_DIAG_BLOCK_NAME "fwdiag"
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#define IFX_CFG_FLASH_FIRMWARE_DIAG_START_ADDR 0xB03FFC00
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#define IFX_CFG_FLASH_FIRMWARE_DIAG_SIZE 0x0200
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#define IFX_CFG_FLASH_FIRMWARE_DIAG_END_ADDR 0xB03FFDFF
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#define IFX_CFG_FLASH_CALIBRATION_CFG_BLOCK_NAME "calibration"
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#define IFX_CFG_FLASH_CALIBRATION_CFG_START_ADDR 0xB03FFE00
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#define IFX_CFG_FLASH_CALIBRATION_CFG_SIZE 0x0200
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#define IFX_CFG_FLASH_CALIBRATION_CFG_END_ADDR 0xB03FFFFF
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#define IFX_CFG_FLASH_END_ADDR 0xB03FFFFF
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//8MB flash definition
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#elif (IFX_CONFIG_FLASH_SIZE == 8)
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#define IFX_CFG_FLASH_PARTITIONS_INFO \
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"part0_begin=0xB0000000\0" \
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"part1_begin=0xB0080000\0" \
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"part2_begin=0xB0280000\0" \
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"part3_begin=0xB0790000\0" \
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"part4_begin=0xB07A0000\0" \
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"part5_begin=0xB07E0000\0" \
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"total_part=6\0"
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#define IFX_CFG_FLASH_DATA_BLOCKS_INFO \
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"data_block0=" IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "\0" \
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"data_block1=" IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "\0" \
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"data_block2=" IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "\0" \
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"data_block3=" IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "\0" \
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"data_block4=" IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "\0" \
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"data_block5=" IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "\0" \
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"total_db=6\0"
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#define IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "uboot"
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#define IFX_CFG_FLASH_UBOOT_IMAGE_START_ADDR 0xB0000000
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#define IFX_CFG_FLASH_UBOOT_IMAGE_END_ADDR 0xB007FFFF
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#define IFX_CFG_FLASH_UBOOT_IMAGE_SIZE 0x00080000
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#define IFX_CFG_FLASH_UBOOT_IMAGE_MTDBLOCK_NAME "/dev/mtdblock0"
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#define IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "kernel"
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#define IFX_CFG_FLASH_KERNEL_IMAGE_START_ADDR 0xB0080000
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#define IFX_CFG_FLASH_KERNEL_IMAGE_SIZE 0x200000
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#define IFX_CFG_FLASH_KERNEL_IMAGE_END_ADDR 0xB017FFFF
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#define IFX_CFG_FLASH_KERNEL_IMAGE_MTDBLOCK_NAME "/dev/mtdblock1"
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "rootfs"
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_START_ADDR 0xB0280000
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_SIZE 0x00510000
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_END_ADDR 0xB078FFFF
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#define IFX_CFG_FLASH_ROOTFS_IMAGE_MTDBLOCK_NAME "/dev/mtdblock2"
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#define IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "sysconfig"
|
||||
#define IFX_CFG_FLASH_SYSTEM_CFG_START_ADDR 0xB0790000
|
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#define IFX_CFG_FLASH_SYSTEM_CFG_SIZE 0x10000
|
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#define IFX_CFG_FLASH_SYSTEM_CFG_END_ADDR 0xB079FFFF
|
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#define IFX_CFG_FLASH_SYSTEM_CFG_MTDBLOCK_NAME "/dev/mtdblock3"
|
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|
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "firmware"
|
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_START_ADDR 0xB07A0000
|
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_SIZE 0x40000
|
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_END_ADDR 0xB07DFFFF
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#define IFX_CFG_FLASH_FIRMWARE_IMAGE_MTDBLOCK_NAME "/dev/mtdblock4"
|
||||
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#define IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "ubootconfig"
|
||||
#define IFX_CFG_FLASH_UBOOT_CFG_START_ADDR 0xB0020000
|
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#define IFX_CFG_FLASH_UBOOT_CFG_END_ADDR 0xB002FFFF
|
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#define IFX_CFG_FLASH_UBOOT_CFG_SIZE 0x10000
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#define IFX_CFG_FLASH_UBOOT_CFG_MTDBLOCK_NAME "/dev/mtdblock5"
|
||||
|
||||
#define IFX_CFG_FLASH_END_ADDR 0xB07FFFFF
|
||||
#else
|
||||
#error "ERROR!! Define flash size first!"
|
||||
#endif
|
||||
/* End of Board specific configurations
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#endif
|
||||
@@ -1,94 +0,0 @@
|
||||
/* ============================================================================
|
||||
* Copyright (C) 2003[- 2004] ? Infineon Technologies AG.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ============================================================================
|
||||
*
|
||||
* ============================================================================
|
||||
*
|
||||
* This document contains proprietary information belonging to Infineon
|
||||
* Technologies AG. Passing on and copying of this document, and communication
|
||||
* of its contents is not permitted without prior written authorisation.
|
||||
*
|
||||
* ============================================================================
|
||||
*
|
||||
* File Name: ifx_extra_env.h
|
||||
* Author : Mars Lin (mars.lin@infineon.com)
|
||||
* Date:
|
||||
*
|
||||
* ===========================================================================
|
||||
*
|
||||
* Project:
|
||||
* Block:
|
||||
*
|
||||
* ===========================================================================
|
||||
* Contents: This file contains the data structures and definitions used
|
||||
* by the core iptables and the sip alg modules.
|
||||
* ===========================================================================
|
||||
* References:
|
||||
*/
|
||||
"mem=" MK_STR(IFX_CONFIG_MEMORY_SIZE) "M\0"
|
||||
"ipaddr=" IFX_CFG_UBOOT_DEFAULT_CFG_IPADDR "\0"
|
||||
"serverip=" IFX_CFG_UBOOT_DEFAULT_CFG_SERVERIP "\0"
|
||||
"ethaddr=" IFX_CFG_UBOOT_DEFAULT_CFG_ETHADDR "\0"
|
||||
"netdev=eth0\0"
|
||||
"baudrate=" IFX_CFG_UBOOT_DEFAULT_CFG_BAUDRATE "\0"
|
||||
"loadaddr=" IFX_CFG_UBOOT_LOAD_ADDRESS "\0"
|
||||
"rootpath=/tftpboot/nfsrootfs\0"
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0"
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0"
|
||||
"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):on\0"
|
||||
"addmisc=setenv bootargs $(bootargs) console=ttyS1,$(baudrate) ethaddr=$(ethaddr) mem=$(mem) panic=1\0"
|
||||
"flash_nfs=run nfsargs addip addmisc;bootm $(kernel_addr)\0"
|
||||
"ramdisk_addr=B0100000\0"
|
||||
"flash_self=run ramargs addip addmisc;bootm $(kernel_addr) $(ramdisk_addr)\0"
|
||||
"bootfile=uImage\0"
|
||||
"net_nfs=tftp $(loadaddr) $(bootfile);run nfsargs addip addmisc;bootm\0"
|
||||
"net_flash=tftp $(loadaddr) $(bootfile); run flashargs addip addmisc; bootm\0"
|
||||
"u-boot=u-boot.ifx\0"
|
||||
"jffs2fs=jffs2.img\0"
|
||||
"rootfs=rootfs.img\0"
|
||||
"firmware=firmware.img\0"
|
||||
"load=tftp $(loadaddr) $(u-boot)\0"
|
||||
"update=protect off 1:0-2;era 1:0-2;cp.b $(loadaddr) B0000000 $(filesize)\0"
|
||||
"flashargs=setenv bootargs root=/dev/mtdblock2 ro rootfstype=squashfs\0"
|
||||
"mtdargs=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"
|
||||
"flash_flash=run flashargs addip addmisc; bootm $(f_kernel_addr)\0"
|
||||
"net_mtd=tftp $(loadaddr) $(bootfile); run mtdargs addip addmisc; bootm\0"
|
||||
"flash_mtd=run mtdargs addip addmisc; bootm $(f_kernel_addr)\0"
|
||||
"update_uboot=tftpboot $(loadaddr) $(u-boot);upgrade uboot $(loadaddr) $(filesize) 0\0"
|
||||
"update_kernel=tftpboot $(loadaddr) $(bootfile);upgrade kernel $(loadaddr) $(filesize) 0\0"
|
||||
"update_rootfs=tftpboot $(loadaddr) $(rootfs); upgrade rootfs $(loadaddr) $(filesize) 0\0"
|
||||
"update_rootfs_1=tftpboot $(loadaddr) $(rootfs); erase 1:47-132; cp.b $(loadaddr) $(f_rootfs_addr) $(filesize)\0"
|
||||
"update_jffs2=tftpboot $(loadaddr) $(rootfs); upgrade rootfs $(loadaddr) $(filesize) 0\0"
|
||||
"update_jffs2_1=tftpboot $(loadaddr) $(jffs2fs); erase 1:47-132; cp.b $(loadaddr) $(f_rootfs_addr) $(filesize)\0"
|
||||
"update_firmware=tftpboot $(loadaddr) $(firmware);upgrade firmware $(loadaddr) $(filesize) 0\0"
|
||||
"reset_uboot_config=erase " MK_STR(IFX_CFG_FLASH_UBOOT_CFG_START_ADDR) " " MK_STR(IFX_CFG_FLASH_UBOOT_CFG_END_ADDR) "\0"
|
||||
IFX_CFG_FLASH_PARTITIONS_INFO
|
||||
"flash_end=" MK_STR(IFX_CFG_FLASH_END_ADDR) "\0"
|
||||
IFX_CFG_FLASH_DATA_BLOCKS_INFO
|
||||
"f_uboot_addr=" MK_STR(IFX_CFG_FLASH_UBOOT_IMAGE_START_ADDR) "\0"
|
||||
"f_uboot_size=" MK_STR(IFX_CFG_FLASH_UBOOT_IMAGE_SIZE) "\0"
|
||||
"f_ubootconfig_addr=" MK_STR(IFX_CFG_FLASH_UBOOT_CFG_START_ADDR) "\0"
|
||||
"f_ubootconfig_size=" MK_STR(IFX_CFG_FLASH_UBOOT_CFG_SIZE) "\0"
|
||||
"f_ubootconfig_end=" MK_STR(IFX_CFG_FLASH_UBOOT_CFG_END_ADDR) "\0"
|
||||
"f_kernel_addr=" MK_STR(IFX_CFG_FLASH_KERNEL_IMAGE_START_ADDR) "\0"
|
||||
"f_kernel_size=" MK_STR(IFX_CFG_FLASH_KERNEL_IMAGE_SIZE) "\0"
|
||||
"f_kernel_end=" MK_STR(IFX_CFG_FLASH_KERNEL_IMAGE_END_ADDR) "\0"
|
||||
"f_rootfs_addr=" MK_STR(IFX_CFG_FLASH_ROOTFS_IMAGE_START_ADDR) "\0"
|
||||
"f_rootfs_size=" MK_STR(IFX_CFG_FLASH_ROOTFS_IMAGE_SIZE) "\0"
|
||||
"f_rootfs_end=" MK_STR(IFX_CFG_FLASH_ROOTFS_IMAGE_END_ADDR) "\0"
|
||||
"f_firmware_addr=" MK_STR(IFX_CFG_FLASH_FIRMWARE_IMAGE_START_ADDR) "\0"
|
||||
"f_firmware_size=" MK_STR(IFX_CFG_FLASH_FIRMWARE_IMAGE_SIZE) "\0"
|
||||
"f_sysconfig_addr=" MK_STR(IFX_CFG_FLASH_SYSTEM_CFG_START_ADDR) "\0"
|
||||
"f_sysconfig_size=" MK_STR(IFX_CFG_FLASH_SYSTEM_CFG_SIZE) "\0"
|
||||
/*
|
||||
"f_fwdiag_addr=" MK_STR(IFX_CFG_FLASH_FIRMWARE_DIAG_START_ADDR) "\0"
|
||||
"f_fwdiag_size=" MK_STR(IFX_CFG_FLASH_FIRMWARE_DIAG_SIZE) "\0"
|
||||
"f_calibration_addr=" MK_STR(IFX_CFG_FLASH_CALIBRATION_CFG_START_ADDR) "\0"
|
||||
"f_calibration_size=" MK_STR(IFX_CFG_FLASH_CALIBRATION_CFG_SIZE) "\0"
|
||||
#if (IFX_CONFIG_FLASH_SIZE == 4) || (IFX_CONFIG_FLASH_SIZE == 8)
|
||||
"f_voip_addr=" MK_STR(IFX_CFG_FLASH_VOIP_CFG_START_ADDR) "\0"
|
||||
"f_voip_size=" MK_STR(IFX_CFG_FLASH_VOIP_CFG_SIZE) "\0"
|
||||
#endif
|
||||
*/
|
||||
Reference in New Issue
Block a user