SW/openwrt
2
0
Fork 0
forked from Ivasoft/openwrt
Code Pull Requests Activity

ar71xx: use ath79_setup_qca955x_eth_cfg helper for QCA955x based boards

Browse Source 
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 41627
This commit is contained in:
Gabor Juhos
2014-07-13 19:44:00 +00:00
parent c4c25e741e
commit 26b39cc580
5 changed files with 58 additions and 138 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
View File

@@ -182,23 +182,6 @@ static struct mdio_board_info archer_c7_mdio0_info[] = {
},
};
static void __init archer_c7_gmac_setup(void)
{
void __iomem *base;
u32 t;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
t |= QCA955X_ETH_CFG_RGMII_EN;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init common_setup(bool pcie_slot)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
@@ -227,7 +210,7 @@ static void __init common_setup(bool pcie_slot)
ARRAY_SIZE(archer_c7_mdio0_info));
ath79_register_mdio(0, 0x0);
archer_c7_gmac_setup();
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;

19
target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c
View File

@@ -187,23 +187,6 @@ static void nbg6716_get_mac(const char *name, char *mac)
pr_err("no MAC address found for %s\n", name);
}
static void __init nbg6716_gmac_setup(void)
{
void __iomem *base;
u32 t;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
t |= QCA955X_ETH_CFG_RGMII_EN;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init nbg6716_common_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1f050000);
@@ -228,7 +211,7 @@ static void __init nbg6716_common_setup(void)
ath79_register_wmac(art + NBG6716_WMAC_CALDATA_OFFSET, tmpmac);
nbg6716_gmac_setup();
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);

19
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c
View File

@@ -164,23 +164,6 @@ static struct mdio_board_info wr1043nd_v2_mdio0_info[] = {
},
};
static void __init wr1043nd_v2_gmac_setup(void)
{
void __iomem *base;
u32 t;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
t |= QCA955X_ETH_CFG_RGMII_EN;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init tl_wr1043nd_v2_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
@@ -202,7 +185,7 @@ static void __init tl_wr1043nd_v2_setup(void)
ARRAY_SIZE(wr1043nd_v2_mdio0_info));
ath79_register_mdio(0, 0x0);
wr1043nd_v2_gmac_setup();
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;

19
target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c
View File

@@ -136,23 +136,6 @@ static struct mdio_board_info wlr8100_mdio0_info[] = {
},
};
static void __init wlr8100_gmac_setup(void)
{
void __iomem *base;
u32 t;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
t |= QCA955X_ETH_CFG_RGMII_EN;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init wlr8100_common_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
@@ -169,7 +152,7 @@ static void __init wlr8100_common_setup(void)
ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL);
wlr8100_gmac_setup();
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);