forked from Ivasoft/DSView
253 lines
8.7 KiB
Python
253 lines
8.7 KiB
Python
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2024 DreamSourceLab <support@dreamsourcelab.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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##
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## 2024/7/5 DreamSourceLab : Read data only when the clock line is high
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##
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import sigrokdecode as srd
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'''
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'''
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class ChannelError(Exception):
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pass
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'C2'
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name = 'C2 interface'
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longname = 'Silabs C2 Interface'
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desc = 'Half-duplex, synchronous, serial bus.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = ['C2']
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tags = ['Embedded/mcu']
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channels = (
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{'id': 'c2ck', 'type': 0, 'name': 'c2ck', 'desc': 'Clock', 'idn':'dec_c2_chan_c2ck'},
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{'id': 'c2d', 'type': 0, 'name': 'c2d', 'desc': 'Data', 'idn':'dec_c2_chan_c2d'},
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)
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optional_channels = ()
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annotations = (
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('106', 'raw-Data', 'raw data'),
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('106', 'c2-data', 'c2 data'),
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('warnings', 'Warnings'),
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)
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annotation_rows = (
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('raw-Data', 'raw data', (0,)),
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('c2-data', 'c2 data', (1,)),
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('warnings', 'Warnings', (2,)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.samplerate = None
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self.state= 'reset'
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self.bitcount = 0
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self.c2_data = 0
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self.data=0
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self.have_c2ck = self.have_c2d = None
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self.ins= None
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self.start_first_sample = 0
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self.data_first_sample = 0
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self.data_len=0
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self.remain_data=0
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def metadata(self, key, value):
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if key == srd.SRD_CONF_SAMPLERATE:
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self.samplerate = value
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def decode(self):
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if not self.has_channel(0):
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raise ChannelError('CLK pin required.')
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self.have_c2d = self.has_channel(1)
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if not self.have_c2d:
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raise ChannelError('C2D pins required.')
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#
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tf=0
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tr=0
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while True:
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(c2ck, c2d) = self.wait({ 0 : 'e' })
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if c2ck == 0:
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tf = self.samplenum
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else:
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tr = self.samplenum
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interval = (tr - tf) * 1000 * 1000 / self.samplerate #us
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if interval > 20:
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self.put(tf, tr, self.out_ann, [0, [ 'Reset','R']])
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self.state = 'start'
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elif self.state == 'start':
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self.put(tf, tr, self.out_ann, [0, [ 'Start','S']])
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self.start_first_sample = tf
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self.state = 'ins'
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ss = tr
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self.ins = 0
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self.bitcount = 0
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elif self.state == 'ins':
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self.ins |= c2d << self.bitcount
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self.bitcount += 1
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if self.bitcount >= 2:
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self.put(ss, self.samplenum, self.out_ann, [0, [ '%1d'%self.ins]])
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if self.ins == 0 :
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self.state = 'Data Read Len'
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self.data_len = 0
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self.remain_data = 0
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elif self.ins == 1:
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self.state = 'Data Write Len'
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self.data_len = 0
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self.remain_data = 0
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elif self.ins == 2:
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self.state = 'Address Read'
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elif self.ins == 3:
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self.state = 'Address Write'
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ss = tr
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self.c2_data = 0
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self.bitcount = 0
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elif self.state == 'Data Read Len':
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self.c2_data |= c2d <<self.bitcount
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self.bitcount += 1
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if self.bitcount >= 2:
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self.put(ss, self.samplenum, self.out_ann, [0, [ '%01d'%self.c2_data]])
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self.state = 'Read Wait'
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self.data_len = self.c2_data + 1
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self.remain_data = self.data_len
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ss = tr
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elif self.state == 'Read Wait':
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self.put(ss, self.samplenum, self.out_ann, [0, ['Wait','W']])
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self.state = 'Data Read'
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self.data = 0
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ss = tr
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self.c2_data = 0
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self.bitcount = 0
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elif self.state == 'Data Read':
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self.c2_data |= c2d << self.bitcount
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self.bitcount += 1
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if self.bitcount >= 8:
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self.put(ss, tr, self.out_ann, [0, ['%02X' % self.c2_data]])
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self.data |= self.c2_data << ((self.data_len - self.remain_data) * 8)
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ss = tr
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self.c2_data = 0
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self.bitcount = 0
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self.remain_data -= 1
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if self.remain_data == 0:
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self.state = 'End'
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elif self.state == 'Data Write Len':
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self.c2_data |= c2d << self.bitcount
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self.bitcount += 1
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if self.bitcount >= 2:
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self.put(ss, self.samplenum, self.out_ann, [0, ['%01d'%self.c2_data]])
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self.state='Data Write'
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self.data_len = self.c2_data + 1
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self.remain_data = self.data_len
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self.data = 0
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ss = tr
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self.c2_data = 0
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self.bitcount = 0
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elif self.state == 'Data Write':
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self.c2_data |= c2d <<self.bitcount
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self.bitcount += 1
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if self.bitcount >= 8:
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self.put(ss, tr, self.out_ann, [0, ['%02X' % self.c2_data]])
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self.data |= self.c2_data << ((self.data_len - self.remain_data) * 8)
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ss = tr
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self.c2_data = 0
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self.bitcount = 0
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self.remain_data -= 1
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if self.remain_data ==0:
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self.state='Write Wait'
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elif self.state == 'Write Wait':
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self.put(ss, self.samplenum, self.out_ann, [0, ['Wait','W']])
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self.state = 'End'
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ss = tr
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elif self.state == 'Address Write':
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self.c2_data |= c2d << self.bitcount
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self.bitcount += 1
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if self.bitcount >= 8:
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self.put(ss, self.samplenum, self.out_ann, [0, ['%02X' % self.c2_data]])
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self.state = 'End'
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ss = tr
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elif self.state == 'Address Read':
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self.c2_data |= c2d << self.bitcount
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self.bitcount += 1
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if self.bitcount >= 8:
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self.put(ss, self.samplenum, self.out_ann, [0, ['%02X' % self.c2_data]])
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self.state = 'End'
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ss = tr
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elif self.state == 'End':
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self.put(ss, self.samplenum, self.out_ann, [0, [ 'End','E']])
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if self.ins == 0:
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self.put(self.start_first_sample, self.samplenum, self.out_ann, [1, [ 'ReadData(%01d)=0x%02X'%(self.data_len,self.data)]])
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elif self.ins == 1:
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self.put(self.start_first_sample, self.samplenum, self.out_ann, [1, [ 'WriteData(0x%02X,%01d)'%(self.data,self.data_len)]])
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elif self.ins == 2:
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self.put(self.start_first_sample, self.samplenum, self.out_ann, [1, [ 'ReadAddress()=0x%02X'%self.c2_data]])
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elif self.ins == 3:
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self.put(self.start_first_sample, self.samplenum, self.out_ann, [1, [ 'WriteAddress(0x%02X)'%self.c2_data]])
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self.state = 'start'
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