From fbbd96711e4dfbad8acb632e9779fc80ccae64fc Mon Sep 17 00:00:00 2001
From: DreamSourceLab <support@dreamsourcelab.com>
Date: Fri, 16 Jun 2023 20:04:28 +0800
Subject: [PATCH] add setting for slow acquisition

---
 libsigrok4DSL/hardware/DSL/dsl.c | 2 ++
 libsigrok4DSL/hardware/DSL/dsl.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/libsigrok4DSL/hardware/DSL/dsl.c b/libsigrok4DSL/hardware/DSL/dsl.c
index b8987bb7..9aa8fdfb 100644
--- a/libsigrok4DSL/hardware/DSL/dsl.c
+++ b/libsigrok4DSL/hardware/DSL/dsl.c
@@ -35,6 +35,7 @@ SR_PRIV int dsl_secuWrite(const struct sr_dev_inst *sdi, uint16_t cmd, uint16_t
 SR_PRIV gboolean dsl_isSecuReady(const struct sr_dev_inst *sdi);
 SR_PRIV gboolean dsl_isSecuPass(const struct sr_dev_inst *sdi);
 SR_PRIV uint16_t dsl_secuRead(const struct sr_dev_inst *sdi);
+static unsigned int to_bytes_per_ms(struct DSL_context *devc);
 
 static const int32_t probeOptions[] = {
     SR_CONF_PROBE_COUPLING,
@@ -1057,6 +1058,7 @@ SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi)
                    (((sdi->mode == ANALOG) || devc->is_loop) << ANALOG_MODE_BIT) +
                    ((devc->filter == SR_FILTER_1T) << FILTER_BIT) +
                    (devc->instant << INSTANT_BIT) +
+                   ((to_bytes_per_ms(devc) < 1024) << SLOW_ACQ_BIT) +
                    ((trigger->trigger_mode == SERIAL_TRIGGER) << STRIG_MODE_BIT) +
                    ((devc->stream) << STREAM_MODE_BIT) +
                    ((devc->test_mode == SR_TEST_LOOPBACK) << LPB_TEST_BIT) +
diff --git a/libsigrok4DSL/hardware/DSL/dsl.h b/libsigrok4DSL/hardware/DSL/dsl.h
index 8a63275c..faedacb3 100644
--- a/libsigrok4DSL/hardware/DSL/dsl.h
+++ b/libsigrok4DSL/hardware/DSL/dsl.h
@@ -96,6 +96,7 @@
 #define ANALOG_MODE_BIT 7
 #define FILTER_BIT 8
 #define INSTANT_BIT 9
+#define SLOW_ACQ_BIT 10
 #define STRIG_MODE_BIT 11
 #define STREAM_MODE_BIT 12
 #define LPB_TEST_BIT 13