From 84040bb276dcfc0ff25bb765a8f2b3592ac07174 Mon Sep 17 00:00:00 2001
From: CJpower <1016753558@qq.com>
Date: Wed, 16 Sep 2020 16:39:31 +0800
Subject: [PATCH] mipi_rffe

---
 .../decoders/{rffe => mipi_rffe}/__init__.py                | 0
 libsigrokdecode4DSL/decoders/{rffe => mipi_rffe}/pd.py      | 6 +++---
 2 files changed, 3 insertions(+), 3 deletions(-)
 rename libsigrokdecode4DSL/decoders/{rffe => mipi_rffe}/__init__.py (100%)
 rename libsigrokdecode4DSL/decoders/{rffe => mipi_rffe}/pd.py (99%)

diff --git a/libsigrokdecode4DSL/decoders/rffe/__init__.py b/libsigrokdecode4DSL/decoders/mipi_rffe/__init__.py
similarity index 100%
rename from libsigrokdecode4DSL/decoders/rffe/__init__.py
rename to libsigrokdecode4DSL/decoders/mipi_rffe/__init__.py
diff --git a/libsigrokdecode4DSL/decoders/rffe/pd.py b/libsigrokdecode4DSL/decoders/mipi_rffe/pd.py
similarity index 99%
rename from libsigrokdecode4DSL/decoders/rffe/pd.py
rename to libsigrokdecode4DSL/decoders/mipi_rffe/pd.py
index b3c8378e..a8673d03 100644
--- a/libsigrokdecode4DSL/decoders/rffe/pd.py
+++ b/libsigrokdecode4DSL/decoders/mipi_rffe/pd.py
@@ -75,13 +75,13 @@ proto = {
 
 class Decoder(srd.Decoder):
     api_version = 3
-    id = 'rffe'
-    name = 'RFFE'
+    id = 'mipi_rffe'
+    name = 'MIPI_RFFE'
     longname = 'RF Front-End Control Interface'
     desc = 'Two-wire, single-master, serial bus.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['rffe']
+    outputs = ['mipi_rffe']
     tags = ['Embedded/industrial']
     channels = (
         {'id': 'sclk', 'type': 8, 'name': 'SCLK', 'desc': 'Serial clock line'},