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Add 32 channels trigger support

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This commit is contained in:
DreamSourceLab
2020-01-08 10:49:11 +08:00
parent caad239315
commit 7328b0b2cc
20 changed files with 777 additions and 367 deletions
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191
libsigrok4DSL/hardware/DSL/dsl.c
View File

@@ -63,7 +63,9 @@ const char *probeMapUnits[] = {
static const char *probe_names[] = {
"0", "1", "2", "3", "4", "5", "6", "7",
"8", "9", "10", "11", "12", "13", "14", "15",
"8", "9", "10", "11", "12", "13", "14", "15",
"16", "17", "18", "19", "20", "21", "22", "23",
"24", "25", "26", "27", "28", "29", "30", "31",
NULL,
};
@@ -701,6 +703,7 @@ SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi)
struct sr_usb_dev_inst *usb;
struct libusb_device_handle *hdl;
struct DSL_setting setting;
struct DSL_setting_ext32 setting_ext32;
int ret;
int transferred;
int i;
@@ -712,6 +715,8 @@ SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi)
struct ctl_wr_cmd wr_cmd;
struct ctl_rd_cmd rd_cmd;
uint8_t rd_cmd_data;
gboolean qutr_trig;
gboolean half_trig;
devc = sdi->priv;
usb = sdi->conn;
@@ -727,7 +732,11 @@ SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi)
setting.dso_count_header = 0x0902;
setting.trig_header = 0x40a0;
setting.end_sync = 0xfa5afa5a;
setting.misc_align = 0xffff;
setting_ext32.sync = 0xf5a5f5a5;
setting_ext32.trig_header = 0x6060;
setting_ext32.align_bytes = 0xffff;
setting_ext32.end_sync = 0xfa5afa5a;
// basic configuration
setting.mode = (trigger->trigger_en << TRIG_EN_BIT) +
@@ -735,8 +744,8 @@ SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi)
(devc->clock_edge << CLK_EDGE_BIT) +
(devc->rle_mode << RLE_MODE_BIT) +
((sdi->mode == DSO) << DSO_MODE_BIT) +
(((devc->cur_samplerate == (2 * channel_modes[devc->ch_mode].hw_max_samplerate)) && sdi->mode != DSO) << HALF_MODE_BIT) +
((devc->cur_samplerate == (4 * channel_modes[devc->ch_mode].hw_max_samplerate)) << QUAR_MODE_BIT) +
((devc->cur_samplerate == devc->profile->dev_caps.half_samplerate) << HALF_MODE_BIT) +
((devc->cur_samplerate == devc->profile->dev_caps.quarter_samplerate) << QUAR_MODE_BIT) +
((sdi->mode == ANALOG) << ANALOG_MODE_BIT) +
((devc->filter == SR_FILTER_1T) << FILTER_BIT) +
(devc->instant << INSTANT_BIT) +
@@ -778,66 +787,39 @@ SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi)
setting.tpos_h = tmp_u32 >> 16;
// trigger global settings
setting.trig_glb = ((ch_num & 0xf) << 4) +
trigger->trigger_stages;
setting.trig_glb = ((ch_num & 0x1f) << 8) +
(trigger->trigger_stages & 0x00ff);
// channel enable mapping
setting.ch_en = 0;
setting.ch_en_l = 0;
setting.ch_en_h = 0;
for (l = sdi->channels; l; l = l->next) {
struct sr_channel *probe = (struct sr_channel *)l->data;
setting.ch_en += probe->enabled << probe->index;
if (probe->index < 16)
setting.ch_en_l += probe->enabled << probe->index;
else
setting.ch_en_h += probe->enabled << (probe->index - 16);
}
// trigger advanced configuration
if (trigger->trigger_mode == SIMPLE_TRIGGER) {
setting.trig_mask0[0] = ds_trigger_get_mask0(TriggerStages);
setting.trig_mask1[0] = ds_trigger_get_mask1(TriggerStages);
qutr_trig = !(devc->profile->dev_caps.feature_caps & CAPS_FEATURE_USB30) && (setting.mode & (1 << QUAR_MODE_BIT));
half_trig = (!(devc->profile->dev_caps.feature_caps & CAPS_FEATURE_USB30) && setting.mode & (1 << HALF_MODE_BIT)) ||
((devc->profile->dev_caps.feature_caps & CAPS_FEATURE_USB30) && setting.mode & (1 << QUAR_MODE_BIT));
setting.trig_value0[0] = ds_trigger_get_value0(TriggerStages);
setting.trig_value1[0] = ds_trigger_get_value1(TriggerStages);
setting.trig_mask0[0] = ds_trigger_get_mask0(TriggerStages, TriggerProbes-1, 0, qutr_trig, half_trig);
setting.trig_mask1[0] = ds_trigger_get_mask1(TriggerStages, TriggerProbes-1, 0, qutr_trig, half_trig);
setting.trig_value0[0] = ds_trigger_get_value0(TriggerStages, TriggerProbes-1, 0, qutr_trig, half_trig);
setting.trig_value1[0] = ds_trigger_get_value1(TriggerStages, TriggerProbes-1, 0, qutr_trig, half_trig);
setting.trig_edge0[0] = ds_trigger_get_edge0(TriggerStages, TriggerProbes-1, 0, qutr_trig, half_trig);
setting.trig_edge1[0] = ds_trigger_get_edge1(TriggerStages, TriggerProbes-1, 0, qutr_trig, half_trig);
setting.trig_edge0[0] = ds_trigger_get_edge0(TriggerStages);
setting.trig_edge1[0] = ds_trigger_get_edge1(TriggerStages);
if (setting.mode & (1 << QUAR_MODE_BIT)) {
setting.trig_mask0[0] = ((setting.trig_mask0[0] & 0x0f) << 12) +
((setting.trig_mask0[0] & 0x0f) << 8) +
((setting.trig_mask0[0] & 0x0f) << 4) +
((setting.trig_mask0[0] & 0x0f) << 0);
setting.trig_mask1[0] = ((setting.trig_mask1[0] & 0x0f) << 12) +
((setting.trig_mask1[0] & 0x0f) << 8) +
((setting.trig_mask1[0] & 0x0f) << 4) +
((setting.trig_mask1[0] & 0x0f) << 0);
setting.trig_value0[0] = ((setting.trig_value0[0] & 0x0f) << 12) +
((setting.trig_value0[0] & 0x0f) << 8) +
((setting.trig_value0[0] & 0x0f) << 4) +
((setting.trig_value0[0] & 0x0f) << 0);
setting.trig_value1[0] = ((setting.trig_value1[0] & 0x0f) << 12) +
((setting.trig_value1[0] & 0x0f) << 8) +
((setting.trig_value1[0] & 0x0f) << 4) +
((setting.trig_value1[0] & 0x0f) << 0);
setting.trig_edge0[0] = ((setting.trig_edge0[0] & 0x0f) << 12) +
((setting.trig_edge0[0] & 0x0f) << 8) +
((setting.trig_edge0[0] & 0x0f) << 4) +
((setting.trig_edge0[0] & 0x0f) << 0);
setting.trig_edge1[0] = ((setting.trig_edge1[0] & 0x0f) << 12) +
((setting.trig_edge1[0] & 0x0f) << 8) +
((setting.trig_edge1[0] & 0x0f) << 4) +
((setting.trig_edge1[0] & 0x0f) << 0);
} else if (setting.mode & (1 << HALF_MODE_BIT)) {
setting.trig_mask0[0] = ((setting.trig_mask0[0] & 0xff) << 8) +
((setting.trig_mask0[0] & 0xff) << 0);
setting.trig_mask1[0] = ((setting.trig_mask1[0] & 0xff) << 8) +
((setting.trig_mask1[0] & 0xff) << 0);
setting.trig_value0[0] = ((setting.trig_value0[0] & 0xff) << 8) +
((setting.trig_value0[0] & 0xff) << 0);
setting.trig_value1[0] = ((setting.trig_value1[0] & 0xff) << 8) +
((setting.trig_value1[0] & 0xff) << 0);
setting.trig_edge0[0] = ((setting.trig_edge0[0] & 0xff) << 8) +
((setting.trig_edge0[0] & 0xff) << 0);
setting.trig_edge1[0] = ((setting.trig_edge1[0] & 0xff) << 8) +
((setting.trig_edge1[0] & 0xff) << 0);
}
setting_ext32.trig_mask0[0] = ds_trigger_get_mask0(TriggerStages, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting_ext32.trig_mask1[0] = ds_trigger_get_mask1(TriggerStages, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting_ext32.trig_value0[0] = ds_trigger_get_value0(TriggerStages, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting_ext32.trig_value1[0] = ds_trigger_get_value1(TriggerStages, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting_ext32.trig_edge0[0] = ds_trigger_get_edge0(TriggerStages, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting_ext32.trig_edge1[0] = ds_trigger_get_edge1(TriggerStages, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting.trig_logic0[0] = (trigger->trigger_logic[TriggerStages] << 1) + trigger->trigger0_inv[TriggerStages];
setting.trig_logic1[0] = (trigger->trigger_logic[TriggerStages] << 1) + trigger->trigger1_inv[TriggerStages];
@@ -847,13 +829,18 @@ SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi)
for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
setting.trig_mask0[i] = 0xffff;
setting.trig_mask1[i] = 0xffff;
setting.trig_value0[i] = 0;
setting.trig_value1[i] = 0;
setting.trig_edge0[i] = 0;
setting.trig_edge1[i] = 0;
setting_ext32.trig_mask0[i] = 0xffff;
setting_ext32.trig_mask1[i] = 0xffff;
setting_ext32.trig_value0[i] = 0;
setting_ext32.trig_value1[i] = 0;
setting_ext32.trig_edge0[i] = 0;
setting_ext32.trig_edge1[i] = 0;
setting.trig_logic0[i] = 2;
setting.trig_logic1[i] = 2;
@@ -861,59 +848,29 @@ SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi)
}
} else {
for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
setting.trig_mask0[i] = ds_trigger_get_mask0(i);
setting.trig_mask1[i] = ds_trigger_get_mask1(i);
setting.trig_value0[i] = ds_trigger_get_value0(i);
setting.trig_value1[i] = ds_trigger_get_value1(i);
setting.trig_edge0[i] = ds_trigger_get_edge0(i);
setting.trig_edge1[i] = ds_trigger_get_edge1(i);
if (setting.mode & (1 << STRIG_MODE_BIT) && i == STriggerDataStage) {
// serial trigger, data mask/value should not be duplicated
qutr_trig = FALSE;
half_trig = FALSE;
} else {
if (setting.mode & (1 << QUAR_MODE_BIT)) {
setting.trig_mask0[i] = ((setting.trig_mask0[i] & 0x0f) << 12) +
((setting.trig_mask0[i] & 0x0f) << 8) +
((setting.trig_mask0[i] & 0x0f) << 4) +
((setting.trig_mask0[i] & 0x0f) << 0);
setting.trig_mask1[i] = ((setting.trig_mask1[i] & 0x0f) << 12) +
((setting.trig_mask1[i] & 0x0f) << 8) +
((setting.trig_mask1[i] & 0x0f) << 4) +
((setting.trig_mask1[i] & 0x0f) << 0);
setting.trig_value0[i] = ((setting.trig_value0[i] & 0x0f) << 12) +
((setting.trig_value0[i] & 0x0f) << 8) +
((setting.trig_value0[i] & 0x0f) << 4) +
((setting.trig_value0[i] & 0x0f) << 0);
setting.trig_value1[i] = ((setting.trig_value1[i] & 0x0f) << 12) +
((setting.trig_value1[i] & 0x0f) << 8) +
((setting.trig_value1[i] & 0x0f) << 4) +
((setting.trig_value1[i] & 0x0f) << 0);
setting.trig_edge0[i] = ((setting.trig_edge0[i] & 0x0f) << 12) +
((setting.trig_edge0[i] & 0x0f) << 8) +
((setting.trig_edge0[i] & 0x0f) << 4) +
((setting.trig_edge0[i] & 0x0f) << 0);
setting.trig_edge1[i] = ((setting.trig_edge1[i] & 0x0f) << 12) +
((setting.trig_edge1[i] & 0x0f) << 8) +
((setting.trig_edge1[i] & 0x0f) << 4) +
((setting.trig_edge1[i] & 0x0f) << 0);
} else if (setting.mode & (1 << HALF_MODE_BIT)) {
setting.trig_mask0[i] = ((setting.trig_mask0[i] & 0xff) << 8) +
((setting.trig_mask0[i] & 0xff) << 0);
setting.trig_mask1[i] = ((setting.trig_mask1[i] & 0xff) << 8) +
((setting.trig_mask1[i] & 0xff) << 0);
setting.trig_value0[i] = ((setting.trig_value0[i] & 0xff) << 8) +
((setting.trig_value0[i] & 0xff) << 0);
setting.trig_value1[i] = ((setting.trig_value1[i] & 0xff) << 8) +
((setting.trig_value1[i] & 0xff) << 0);
setting.trig_edge0[i] = ((setting.trig_edge0[i] & 0xff) << 8) +
((setting.trig_edge0[i] & 0xff) << 0);
setting.trig_edge1[i] = ((setting.trig_edge1[i] & 0xff) << 8) +
((setting.trig_edge1[i] & 0xff) << 0);
}
qutr_trig = !(devc->profile->dev_caps.feature_caps & CAPS_FEATURE_USB30) && (setting.mode & (1 << QUAR_MODE_BIT));
half_trig = (!(devc->profile->dev_caps.feature_caps & CAPS_FEATURE_USB30) && setting.mode & (1 << HALF_MODE_BIT)) ||
((devc->profile->dev_caps.feature_caps & CAPS_FEATURE_USB30) && setting.mode & (1 << QUAR_MODE_BIT));
}
setting.trig_mask0[i] = ds_trigger_get_mask0(i, TriggerProbes-1 , 0, qutr_trig, half_trig);
setting.trig_mask1[i] = ds_trigger_get_mask1(i, TriggerProbes-1, 0, qutr_trig, half_trig);
setting.trig_value0[i] = ds_trigger_get_value0(i, TriggerProbes-1, 0, qutr_trig, half_trig);
setting.trig_value1[i] = ds_trigger_get_value1(i, TriggerProbes-1, 0, qutr_trig, half_trig);
setting.trig_edge0[i] = ds_trigger_get_edge0(i, TriggerProbes-1, 0, qutr_trig, half_trig);
setting.trig_edge1[i] = ds_trigger_get_edge1(i, TriggerProbes-1, 0, qutr_trig, half_trig);
setting_ext32.trig_mask0[i] = ds_trigger_get_mask0(i, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting_ext32.trig_mask1[i] = ds_trigger_get_mask1(i, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting_ext32.trig_value0[i] = ds_trigger_get_value0(i, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting_ext32.trig_value1[i] = ds_trigger_get_value1(i, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting_ext32.trig_edge0[i] = ds_trigger_get_edge0(i, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting_ext32.trig_edge1[i] = ds_trigger_get_edge1(i, 2*TriggerProbes-1, TriggerProbes, qutr_trig, half_trig);
setting.trig_logic0[i] = (trigger->trigger_logic[i] << 1) + trigger->trigger0_inv[i];
setting.trig_logic1[i] = (trigger->trigger_logic[i] << 1) + trigger->trigger1_inv[i];
@@ -956,6 +913,7 @@ SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi)
}
// send bulk data
// setting
ret = libusb_bulk_transfer(hdl, 2 | LIBUSB_ENDPOINT_OUT,
(unsigned char *)&setting,
sizeof(struct DSL_setting),
@@ -969,6 +927,22 @@ SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi)
sizeof(struct DSL_setting), transferred);
return SR_ERR;
}
// setting_ext32
if (devc->profile->dev_caps.feature_caps & CAPS_FEATURE_LA_CH32) {
ret = libusb_bulk_transfer(hdl, 2 | LIBUSB_ENDPOINT_OUT,
(unsigned char *)&setting_ext32,
sizeof(struct DSL_setting_ext32),
&transferred, 1000);
if (ret < 0) {
sr_err("Unable to arm FPGA(setting_ext32) of dsl device: %s.",
libusb_error_name(ret));
return SR_ERR;
} else if (transferred != sizeof(struct DSL_setting_ext32)) {
sr_err("Arm FPGA(setting_ext32) error: expacted transfer size %d; actually %d",
sizeof(struct DSL_setting_ext32), transferred);
return SR_ERR;
}
}
// assert INTRDY high (indicate data end)
wr_cmd.header.dest = DSL_CTL_INTRDY;
@@ -1363,7 +1337,12 @@ SR_PRIV int dsl_config_get(int id, GVariant **data, const struct sr_dev_inst *sd
case SR_CONF_BANDWIDTH:
if (!sdi)
return SR_ERR;
*data = g_variant_new_boolean(devc->profile->dev_caps.feature_caps & CAPS_FEATURE_20M);
*data = g_variant_new_boolean((devc->profile->dev_caps.feature_caps & CAPS_FEATURE_20M) != 0);
break;
case SR_CONF_LA_CH32:
if (!sdi)
return SR_ERR;
*data = g_variant_new_boolean((devc->profile->dev_caps.feature_caps & CAPS_FEATURE_LA_CH32) != 0);
break;
default:
return SR_ERR_NA;

105
libsigrok4DSL/hardware/DSL/dsl.h
View File

@@ -83,7 +83,13 @@
// use ADF4360-7 vco chip
#define CAPS_FEATURE_ADF4360 (1 << 8)
// 20M bandwidth limitation
#define CAPS_FEATURE_20M (1 << 8)
#define CAPS_FEATURE_20M (1 << 9)
// use startup flash (fx3)
#define CAPS_FEATURE_FLASH (1 << 10)
// 32 channels
#define CAPS_FEATURE_LA_CH32 (1 << 11)
// auto tunning vgain
#define CAPS_FEATURE_AUTO_VGAIN (1 << 12)
/* end */
@@ -156,6 +162,7 @@ struct DSL_caps {
uint64_t mode_caps;
uint64_t feature_caps;
uint64_t channels;
uint64_t total_ch_num;
uint64_t hw_depth;
uint64_t dso_depth;
uint8_t intest_channel;
@@ -170,6 +177,8 @@ struct DSL_caps {
uint32_t ref_min;
uint32_t ref_max;
uint16_t default_comb_comp;
uint64_t half_samplerate;
uint64_t quarter_samplerate;
};
struct DSL_profile {
@@ -442,6 +451,7 @@ static const struct DSL_profile supported_DSLogic[] = {
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4) |
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
16,
SR_MB(256),
SR_Mn(2),
DSL_BUFFER100x16,
@@ -455,7 +465,9 @@ static const struct DSL_profile supported_DSLogic[] = {
0,
0,
0,
0}
0,
SR_MHZ(200),
SR_MHZ(400)}
},
{0x2A0E, 0x0003, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic Pro", NULL,
@@ -466,6 +478,7 @@ static const struct DSL_profile supported_DSLogic[] = {
CAPS_FEATURE_SEEP | CAPS_FEATURE_VTH | CAPS_FEATURE_BUF,
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4),
16,
SR_MB(256),
0,
DSL_BUFFER100x16,
@@ -479,7 +492,9 @@ static const struct DSL_profile supported_DSLogic[] = {
0,
0,
0,
0}
0,
SR_MHZ(200),
SR_MHZ(400)}
},
{0x2A0E, 0x0020, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic PLus", NULL,
@@ -490,6 +505,7 @@ static const struct DSL_profile supported_DSLogic[] = {
CAPS_FEATURE_VTH | CAPS_FEATURE_BUF,
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4),
16,
SR_MB(256),
0,
DSL_BUFFER100x16,
@@ -503,7 +519,9 @@ static const struct DSL_profile supported_DSLogic[] = {
0,
0,
0,
0}
0,
SR_MHZ(200),
SR_MHZ(400)}
},
{0x2A0E, 0x0021, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic Basic", NULL,
@@ -514,6 +532,7 @@ static const struct DSL_profile supported_DSLogic[] = {
CAPS_FEATURE_VTH,
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4),
16,
SR_KB(256),
0,
DSL_STREAM20x16,
@@ -527,7 +546,9 @@ static const struct DSL_profile supported_DSLogic[] = {
0,
0,
0,
0}
0,
SR_MHZ(200),
SR_MHZ(400)}
},
{0x2A0E, 0x0029, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic U2Basic", NULL,
@@ -538,6 +559,7 @@ static const struct DSL_profile supported_DSLogic[] = {
CAPS_FEATURE_VTH | CAPS_FEATURE_BUF,
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
(1 << DSL_BUFFER100x16),
16,
SR_MB(64),
0,
DSL_BUFFER100x16,
@@ -551,10 +573,12 @@ static const struct DSL_profile supported_DSLogic[] = {
0,
0,
0,
0}
0,
SR_MHZ(200),
SR_MHZ(400)}
},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
};
static const struct DSL_profile supported_DSCope[] = {
@@ -569,6 +593,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_PREOFF | CAPS_FEATURE_SEEP | CAPS_FEATURE_BUF,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
@@ -582,7 +607,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0004, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope20", NULL,
@@ -593,6 +620,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_SEEP | CAPS_FEATURE_BUF,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
@@ -606,7 +634,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0022, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope B20", NULL,
@@ -617,6 +647,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
@@ -630,7 +661,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0023, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope C20", NULL,
@@ -641,6 +674,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
@@ -654,7 +688,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
@@ -666,6 +702,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF | CAPS_FEATURE_POGOPIN,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
@@ -679,7 +716,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0025, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope C20", NULL,
@@ -690,6 +729,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_KB(256),
SR_Kn(20),
0,
@@ -703,7 +743,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0026, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope U2B20", NULL,
@@ -714,6 +756,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_KB(256),
SR_Kn(20),
0,
@@ -727,7 +770,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-945,
10,
245,
22}
22,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0027, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope U2P20", NULL,
@@ -738,6 +783,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF | CAPS_FEATURE_POGOPIN,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
@@ -751,11 +797,13 @@ static const struct DSL_profile supported_DSCope[] = {
1024-945,
10,
245,
22}
22,
SR_HZ(0),
SR_HZ(0)}
},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
};
static const gboolean default_ms_en[] = {
@@ -883,12 +931,14 @@ struct DSL_setting {
uint16_t tpos_h;
uint16_t trig_glb_header; // 7
uint16_t trig_glb;
uint16_t ch_en_header; // 8
uint16_t ch_en;
uint16_t dso_count_header; // 9-10
uint16_t dso_count_header; // 8-9
uint16_t dso_cnt_l;
uint16_t dso_cnt_h;
uint16_t misc_align;
uint16_t ch_en_header; // 10-11
uint16_t ch_en_l;
uint16_t ch_en_h;
uint16_t fgain_header; // 12
uint16_t fgain;
uint16_t trig_header; // 64
uint16_t trig_mask0[NUM_TRIGGER_STAGES];
@@ -904,6 +954,21 @@ struct DSL_setting {
uint32_t end_sync;
};
struct DSL_setting_ext32 {
uint32_t sync;
uint16_t trig_header; // 96
uint16_t trig_mask0[NUM_TRIGGER_STAGES];
uint16_t trig_mask1[NUM_TRIGGER_STAGES];
uint16_t trig_value0[NUM_TRIGGER_STAGES];
uint16_t trig_value1[NUM_TRIGGER_STAGES];
uint16_t trig_edge0[NUM_TRIGGER_STAGES];
uint16_t trig_edge1[NUM_TRIGGER_STAGES];
uint16_t align_bytes;
uint32_t end_sync;
};
struct DSL_adc_config {
uint8_t dest;
uint8_t cnt;

5
libsigrok4DSL/hardware/DSL/dslogic.c
View File

@@ -662,6 +662,11 @@ static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
return SR_ERR;
*data = g_variant_new_int16(channel_modes[devc->ch_mode].vld_num);
break;
case SR_CONF_TOTAL_CH_NUM:
if (!sdi)
return SR_ERR;
*data = g_variant_new_int16(devc->profile->dev_caps.total_ch_num);
break;
default:
return SR_ERR_NA;
}

11
libsigrok4DSL/libsigrok.h
View File

@@ -118,6 +118,7 @@ enum {
#define DS_MAX_DSO_PROBES_NUM 2
#define TriggerStages 16
#define TriggerProbes 16
#define MaxTriggerProbes 32
#define TriggerCountBits 16
#define STriggerDataStage 3
@@ -857,9 +858,15 @@ enum {
SR_CONF_REF_MIN,
SR_CONF_REF_MAX,
/** Valid channel number */
SR_CONF_TOTAL_CH_NUM,
/** Valid channel number */
SR_CONF_VLD_CH_NUM,
/** 32 channel support */
SR_CONF_LA_CH32,
/** Zero */
SR_CONF_HAVE_ZERO,
SR_CONF_ZERO,
@@ -1254,8 +1261,8 @@ struct ds_trigger {
unsigned char trigger_logic[TriggerStages+1];
unsigned char trigger0_inv[TriggerStages+1];
unsigned char trigger1_inv[TriggerStages+1];
char trigger0[TriggerStages+1][TriggerProbes];
char trigger1[TriggerStages+1][TriggerProbes];
char trigger0[TriggerStages+1][MaxTriggerProbes];
char trigger1[TriggerStages+1][MaxTriggerProbes];
uint32_t trigger0_count[TriggerStages+1];
uint32_t trigger1_count[TriggerStages+1];
};

12
libsigrok4DSL/proto.h
View File

@@ -173,10 +173,10 @@ SR_API int ds_trigger_set_en(uint16_t enable);
SR_API uint16_t ds_trigger_get_en();
SR_API int ds_trigger_set_mode(uint16_t mode);
SR_PRIV uint64_t ds_trigger_get_mask0(uint16_t stage);
SR_PRIV uint64_t ds_trigger_get_value0(uint16_t stage);
SR_PRIV uint64_t ds_trigger_get_edge0(uint16_t stage);
SR_PRIV uint64_t ds_trigger_get_mask1(uint16_t stage);
SR_PRIV uint64_t ds_trigger_get_value1(uint16_t stage);
SR_PRIV uint64_t ds_trigger_get_edge1(uint16_t stage);
SR_PRIV uint16_t ds_trigger_get_mask0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
SR_PRIV uint16_t ds_trigger_get_value0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
SR_PRIV uint16_t ds_trigger_get_edge0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
SR_PRIV uint16_t ds_trigger_get_mask1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
SR_PRIV uint16_t ds_trigger_get_value1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
SR_PRIV uint16_t ds_trigger_get_edge1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
#endif

126
libsigrok4DSL/trigger.c
View File

@@ -58,7 +58,7 @@ SR_API int ds_trigger_init(void)
trigger->trigger_stages = 0;
for (i = 0; i <= TriggerStages; i++) {
for (j = 0; j < TriggerProbes; j++) {
for (j = 0; j < MaxTriggerProbes; j++) {
trigger->trigger0[i][j] = 'X';
trigger->trigger1[i][j] = 'X';
}
@@ -99,7 +99,7 @@ SR_API struct ds_trigger *ds_trigger_get(void)
SR_API int ds_trigger_stage_set_value(uint16_t stage, uint16_t probes, char *trigger0, char *trigger1)
{
assert(stage < TriggerStages);
assert(probes <= TriggerProbes);
assert(probes <= MaxTriggerProbes);
int j;
@@ -113,7 +113,7 @@ SR_API int ds_trigger_stage_set_value(uint16_t stage, uint16_t probes, char *tri
SR_API int ds_trigger_stage_set_logic(uint16_t stage, uint16_t probes, unsigned char trigger_logic)
{
assert(stage < TriggerStages);
assert(probes <= TriggerProbes);
assert(probes <= MaxTriggerProbes);
trigger->trigger_logic[stage] = trigger_logic;
@@ -122,7 +122,7 @@ SR_API int ds_trigger_stage_set_logic(uint16_t stage, uint16_t probes, unsigned
SR_API int ds_trigger_stage_set_inv(uint16_t stage, uint16_t probes, unsigned char trigger0_inv, unsigned char trigger1_inv)
{
assert(stage < TriggerStages);
assert(probes <= TriggerProbes);
assert(probes <= MaxTriggerProbes);
trigger->trigger0_inv[stage] = trigger0_inv;
trigger->trigger1_inv[stage] = trigger1_inv;
@@ -132,7 +132,7 @@ SR_API int ds_trigger_stage_set_inv(uint16_t stage, uint16_t probes, unsigned ch
SR_API int ds_trigger_stage_set_count(uint16_t stage, uint16_t probes, uint32_t trigger0_count, uint32_t trigger1_count)
{
assert(stage < TriggerStages);
assert(probes <= TriggerProbes);
assert(probes <= MaxTriggerProbes);
trigger->trigger0_count[stage] = trigger0_count;
trigger->trigger1_count[stage] = trigger1_count;
@@ -147,7 +147,7 @@ SR_API int ds_trigger_stage_set_count(uint16_t stage, uint16_t probes, uint32_t
*/
SR_API int ds_trigger_probe_set(uint16_t probe, unsigned char trigger0, unsigned char trigger1)
{
assert(probe < TriggerProbes);
assert(probe < MaxTriggerProbes);
trigger->trigger0[TriggerStages][probe] = trigger0;
trigger->trigger1[TriggerStages][probe] = trigger1;
@@ -235,90 +235,168 @@ SR_API int ds_trigger_set_mode(uint16_t mode)
/*
*
*/
SR_PRIV uint64_t ds_trigger_get_mask0(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_mask0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t mask = 0;
uint16_t mask = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
mask = (mask << 1);
mask += ((trigger->trigger0[stage][i] == 'X') | (trigger->trigger0[stage][i] == 'C'));
}
if (qutr_mode)
mask = ((mask & qutr_mask) << (TriggerProbes/4*3)) +
((mask & qutr_mask) << (TriggerProbes/4*2)) +
((mask & qutr_mask) << (TriggerProbes/4*1)) +
((mask & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
mask = ((mask & half_mask) << (TriggerProbes/2*1)) +
((mask & half_mask) << (TriggerProbes/2*0));
return mask;
}
SR_PRIV uint64_t ds_trigger_get_mask1(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_mask1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t mask = 0;
uint16_t mask = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
mask = (mask << 1);
mask += ((trigger->trigger1[stage][i] == 'X') | (trigger->trigger1[stage][i] == 'C'));
}
if (qutr_mode)
mask = ((mask & qutr_mask) << (TriggerProbes/4*3)) +
((mask & qutr_mask) << (TriggerProbes/4*2)) +
((mask & qutr_mask) << (TriggerProbes/4*1)) +
((mask & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
mask = ((mask & half_mask) << (TriggerProbes/2*1)) +
((mask & half_mask) << (TriggerProbes/2*0));
return mask;
}
SR_PRIV uint64_t ds_trigger_get_value0(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_value0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t value = 0;
uint16_t value = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
value = (value << 1);
value += ((trigger->trigger0[stage][i] == '1') | (trigger->trigger0[stage][i] == 'R'));
}
if (qutr_mode)
value = ((value & qutr_mask) << (TriggerProbes/4*3)) +
((value & qutr_mask) << (TriggerProbes/4*2)) +
((value & qutr_mask) << (TriggerProbes/4*1)) +
((value & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
value = ((value & half_mask) << (TriggerProbes/2*1)) +
((value & half_mask) << (TriggerProbes/2*0));
return value;
}
SR_PRIV uint64_t ds_trigger_get_value1(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_value1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t value = 0;
uint16_t value = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
value = (value << 1);
value += ((trigger->trigger1[stage][i] == '1') | (trigger->trigger1[stage][i] == 'R'));
}
if (qutr_mode)
value = ((value & qutr_mask) << (TriggerProbes/4*3)) +
((value & qutr_mask) << (TriggerProbes/4*2)) +
((value & qutr_mask) << (TriggerProbes/4*1)) +
((value & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
value = ((value & half_mask) << (TriggerProbes/2*1)) +
((value & half_mask) << (TriggerProbes/2*0));
return value;
}
SR_PRIV uint64_t ds_trigger_get_edge0(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_edge0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t edge = 0;
uint16_t edge = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
edge = (edge << 1);
edge += ((trigger->trigger0[stage][i] == 'R') | (trigger->trigger0[stage][i] == 'F') |
(trigger->trigger0[stage][i] == 'C'));
}
if (qutr_mode)
edge = ((edge & qutr_mask) << (TriggerProbes/4*3)) +
((edge & qutr_mask) << (TriggerProbes/4*2)) +
((edge & qutr_mask) << (TriggerProbes/4*1)) +
((edge & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
edge = ((edge & half_mask) << (TriggerProbes/2*1)) +
((edge & half_mask) << (TriggerProbes/2*0));
return edge;
}
SR_PRIV uint64_t ds_trigger_get_edge1(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_edge1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t edge = 0;
uint16_t edge = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
edge = (edge << 1);
edge += ((trigger->trigger1[stage][i] == 'R') | (trigger->trigger1[stage][i] == 'F') |
(trigger->trigger1[stage][i] == 'C'));
}
if (qutr_mode)
edge = ((edge & qutr_mask) << (TriggerProbes/4*3)) +
((edge & qutr_mask) << (TriggerProbes/4*2)) +
((edge & qutr_mask) << (TriggerProbes/4*1)) +
((edge & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
edge = ((edge & half_mask) << (TriggerProbes/2*1)) +
((edge & half_mask) << (TriggerProbes/2*0));
return edge;
}