diff --git a/libsigrokdecode4DSL/decoders/ieee488/pd.py b/libsigrokdecode4DSL/decoders/ieee488/pd.py
index 078e0748..70c2d82e 100644
--- a/libsigrokdecode4DSL/decoders/ieee488/pd.py
+++ b/libsigrokdecode4DSL/decoders/ieee488/pd.py
@@ -620,7 +620,8 @@ class Decoder(srd.Decoder):
             # re-use 'iec' decoder logic. Turn ATN to positive logic for
             # easier processing. The data bits get handled during byte
             # accumulation.
-            pins = self.wait(step_wait_conds[step])
+            (dio1,dio2,dio3,dio4,dio5,dio6,dio7,dio8,eoi,dav,nrfd,ndac,ifc,srq,atn,ren,clk)= self.wait(step_wait_conds[step])
+            pins = (dio1,dio2,dio3,dio4,dio5,dio6,dio7,dio8,eoi,dav,nrfd,ndac,ifc,srq,atn,ren,clk)
             data, clk = pins[PIN_DATA], pins[PIN_CLK]
             atn, = self.invert_pins([pins[PIN_ATN]])
 
diff --git a/libsigrokdecode4DSL/decoders/sle44xx/pd.py b/libsigrokdecode4DSL/decoders/sle44xx/pd.py
index 6656cede..fc85f3b8 100644
--- a/libsigrokdecode4DSL/decoders/sle44xx/pd.py
+++ b/libsigrokdecode4DSL/decoders/sle44xx/pd.py
@@ -492,8 +492,7 @@ class Decoder(srd.Decoder):
 
             is_outgoing = self.state == 'OUT'
             is_processing = self.state == 'PROC'
-            pins = self.wait(conditions)
-            io = pins[Pin.IO]
+            (rst,clk,io) = self.wait(conditions)
 
             # Handle RESET conditions, including an optional CLK pulse
             # while RST is asserted.