From 462b4fa10af239b92486242b92bd3f9beed3a4ca Mon Sep 17 00:00:00 2001 From: yunyaobaihong <896458252@qq.com> Date: Mon, 22 Jul 2024 09:32:07 +0800 Subject: [PATCH] Decoder Update : Fixed C2 Frame Error , WS2812 add default color order and Smart QSPI QPP output update --- lang/cn/dec/p.json | 8 +- libsigrokdecode4DSL/decoders/c2/pd.py | 318 ++++++++++-------- .../decoders/rgb_led_ws281x/pd.py | 142 ++++---- libsigrokdecode4DSL/decoders/smart qspi/pd.py | 42 ++- 4 files changed, 275 insertions(+), 235 deletions(-) diff --git a/lang/cn/dec/p.json b/lang/cn/dec/p.json index fedcbc6a..b85f4061 100644 --- a/lang/cn/dec/p.json +++ b/lang/cn/dec/p.json @@ -112,8 +112,12 @@ "text": "DIN数据线" }, { - "id": "dec_rgb_led_ws281x_opt_colors", - "text": "颜色" + "id": "dec_rgb_led_ws281x_opt_default_color_order", + "text": "默认颜色顺序" + }, + { + "id": "dec_rgb_led_ws281x_opt_view_color_order", + "text": "视图颜色顺序" }, { "id": "dec_rgb_led_ws281x_opt_polarity", diff --git a/libsigrokdecode4DSL/decoders/c2/pd.py b/libsigrokdecode4DSL/decoders/c2/pd.py index 099cf37d..fecd2bdc 100644 --- a/libsigrokdecode4DSL/decoders/c2/pd.py +++ b/libsigrokdecode4DSL/decoders/c2/pd.py @@ -1,3 +1,26 @@ +## +## This file is part of the libsigrokdecode project. +## +## Copyright (C) 2024 DreamSourceLab +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +## +## 2024/7/5 DreamSourceLab : Read data only when the clock line is high +## + import sigrokdecode as srd ''' @@ -39,15 +62,16 @@ class Decoder(srd.Decoder): self.samplerate = None self.state= 'reset' self.bitcount = 0 - self.c2data = 0 + self.c2_data = 0 self.data=0 - self.c2dbits = [] - self.ss_block = -1 - self.samplenum = -1 self.have_c2ck = self.have_c2d = None self.ins= None - self.dataLen=0 - self.remainData=0 + + self.start_first_sample = 0 + self.data_first_sample = 0 + + self.data_len=0 + self.remain_data=0 def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) @@ -62,143 +86,167 @@ class Decoder(srd.Decoder): self.have_c2d = self.has_channel(1) if not self.have_c2d: raise ChannelError('C2D pins required.') + # tf=0 tr=0 + while True: - (c2ck,c2d)=self.wait({0:'e'}) - if c2ck == 0: #�½��� - tf=self.samplenum - if self.state == 'dataRead': - if self.bitcount ==0: - ss=tr - self.c2data=0 - self.c2data |= c2d <= 8: - self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]]) - self.bitcount=0 - self.data|=self.c2data<<((self.dataLen-self.remainData)*8) - self.remainData -= 1 - if self.remainData ==0: - self.state = 'end' - elif self.state == 'addressRead': - if self.bitcount ==0: - ss=tr - self.c2data=0 - self.c2data |= c2d <= 8: - self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]]) - self.state = 'end' - elif self.state == 'readWait': - if self.bitcount ==0: - ss=tf - self.bitcount +=1 - if c2d == 1: - self.put(ss, tf, self.out_ann, [0, ['Wait','W']]) - self.bitcount=0 - self.state = 'dataRead' - elif self.state == 'writeWait': - if self.bitcount ==0: - ss=tr - self.bitcount += 1 - if c2d == 1: - self.put(ss, tf, self.out_ann, [0, ['Wait','W']]) - self.state = 'end' - - else: #������ - tr=self.samplenum - interval=(tr-tf)*1000*1000/self.samplerate #us - if interval>20: + (c2ck, c2d) = self.wait({ 0 : 'e' }) + if c2ck == 0: + tf = self.samplenum + else: + tr = self.samplenum + + interval = (tr - tf) * 1000 * 1000 / self.samplerate #us + + if interval > 20: self.put(tf, tr, self.out_ann, [0, [ 'Reset','R']]) - self.state='start' + self.state = 'start' + elif self.state == 'start': self.put(tf, tr, self.out_ann, [0, [ 'Start','S']]) - self.state='ins' - self.bitcount=0 - self.ins=0 - self.data=0 - self.dataLen=0 - ss1=tf + + self.start_first_sample = tf + + self.state = 'ins' + ss = tr + self.ins = 0 + self.bitcount = 0 + elif self.state == 'ins': - if self.bitcount ==0: - ss=tr - self.c2data=0 - self.ins |= c2d <= 2: - (c2ck,c2d)=self.wait({0:'f'}) - if self.ins == 0 : - self.state = 'dataReadLen' - elif self.ins == 2: - self.state = 'addressRead' - elif self.ins == 1: - self.state = 'dataWriteLen' - else: - self.state = 'addressWrite' self.put(ss, self.samplenum, self.out_ann, [0, [ '%1d'%self.ins]]) - self.bitcount=0 - elif self.state == 'addressWrite': - if self.bitcount ==0: - ss=tr - self.c2data=0 - self.c2data |= c2d <= 8: - (c2ck,c2d)=self.wait({0:'f'}) - tf=self.samplenum - self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]]) - self.bitcount=0 - self.state = 'end' - elif self.state == 'dataReadLen': - if self.bitcount ==0: - ss=tr - self.c2data=0 - self.c2data |= c2d <= 2: - self.dataLen=self.c2data+1 - self.remainData=self.dataLen - #(c2ck,c2d)=self.wait({0:'f'}) - self.put(ss, self.samplenum, self.out_ann, [0, [ '%01d'%self.c2data]]) - self.state='readWait' - self.bitcount=0 - elif self.state == 'dataWriteLen': - if self.bitcount ==0: - ss=tr - self.c2data=0 - self.c2data |= c2d <= 2: - self.dataLen=self.c2data+1 - self.remainData=self.dataLen - (c2ck,c2d)=self.wait({0:'f'}) - self.put(ss, self.samplenum, self.out_ann, [0, ['%01d'%self.c2data]]) - self.state='dataWrite' - self.bitcount=0 - self.c2data=0 - elif self.state == 'dataWrite': - if self.bitcount ==0: - ss=tr - self.c2data=0 - self.c2data |= c2d <= 8: - self.put(ss, tr, self.out_ann, [0, ['%02X' % self.c2data]]) - self.bitcount=0 - self.data|=self.c2data<<((self.dataLen-self.remainData)*8) - self.remainData -= 1 - if self.remainData ==0: - self.state='writeWait' - elif self.state == 'end': - self.state='start' - self.put(tf, tr, self.out_ann, [0, [ 'End','E']]) - if self.ins == 0: - self.put(ss1, tr, self.out_ann, [1, [ 'ReadData(%01d)=0x%02X'%(self.dataLen,self.data)]]) - elif self.ins == 1: - self.put(ss1, tr, self.out_ann, [1, [ 'WriteData(0x%02X,%01d)'%(self.data,self.dataLen)]]) - elif self.ins == 2: - self.put(ss1, tr, self.out_ann, [1, [ 'ReadAddress()=0x%02X'%self.c2data]]) - elif self.ins == 3: - self.put(ss1, tr, self.out_ann, [1, [ 'WriteAddress(0x%02X)'%self.c2data]]) + + if self.ins == 0 : + self.state = 'Data Read Len' + self.data_len = 0 + self.remain_data = 0 + elif self.ins == 1: + self.state = 'Data Write Len' + self.data_len = 0 + self.remain_data = 0 + elif self.ins == 2: + self.state = 'Address Read' + elif self.ins == 3: + self.state = 'Address Write' + + ss = tr + self.c2_data = 0 + self.bitcount = 0 + + elif self.state == 'Data Read Len': + self.c2_data |= c2d <= 2: + self.put(ss, self.samplenum, self.out_ann, [0, [ '%01d'%self.c2_data]]) + + self.state = 'Read Wait' + self.data_len = self.c2_data + 1 + self.remain_data = self.data_len + + ss = tr + + elif self.state == 'Read Wait': + self.put(ss, self.samplenum, self.out_ann, [0, ['Wait','W']]) + self.state = 'Data Read' + + self.data = 0 + ss = tr + self.c2_data = 0 + self.bitcount = 0 + + elif self.state == 'Data Read': + self.c2_data |= c2d << self.bitcount + self.bitcount += 1 + + if self.bitcount >= 8: + self.put(ss, tr, self.out_ann, [0, ['%02X' % self.c2_data]]) + + self.data |= self.c2_data << ((self.data_len - self.remain_data) * 8) + + ss = tr + self.c2_data = 0 + self.bitcount = 0 + + self.remain_data -= 1 + if self.remain_data == 0: + self.state = 'End' + + elif self.state == 'Data Write Len': + self.c2_data |= c2d << self.bitcount + self.bitcount += 1 + + if self.bitcount >= 2: + self.put(ss, self.samplenum, self.out_ann, [0, ['%01d'%self.c2_data]]) + + self.state='Data Write' + self.data_len = self.c2_data + 1 + self.remain_data = self.data_len + + self.data = 0 + ss = tr + self.c2_data = 0 + self.bitcount = 0 + + elif self.state == 'Data Write': + self.c2_data |= c2d <= 8: + self.put(ss, tr, self.out_ann, [0, ['%02X' % self.c2_data]]) + + self.data |= self.c2_data << ((self.data_len - self.remain_data) * 8) + + ss = tr + self.c2_data = 0 + self.bitcount = 0 + + self.remain_data -= 1 + + if self.remain_data ==0: + self.state='Write Wait' + elif self.state == 'Write Wait': + self.put(ss, self.samplenum, self.out_ann, [0, ['Wait','W']]) + self.state = 'End' + + ss = tr + + elif self.state == 'Address Write': + self.c2_data |= c2d << self.bitcount + self.bitcount += 1 + + if self.bitcount >= 8: + self.put(ss, self.samplenum, self.out_ann, [0, ['%02X' % self.c2_data]]) + + self.state = 'End' + ss = tr + + elif self.state == 'Address Read': + self.c2_data |= c2d << self.bitcount + self.bitcount += 1 + + if self.bitcount >= 8: + self.put(ss, self.samplenum, self.out_ann, [0, ['%02X' % self.c2_data]]) + + self.state = 'End' + ss = tr + + elif self.state == 'End': + self.put(ss, self.samplenum, self.out_ann, [0, [ 'End','E']]) + + if self.ins == 0: + self.put(self.start_first_sample, self.samplenum, self.out_ann, [1, [ 'ReadData(%01d)=0x%02X'%(self.data_len,self.data)]]) + elif self.ins == 1: + self.put(self.start_first_sample, self.samplenum, self.out_ann, [1, [ 'WriteData(0x%02X,%01d)'%(self.data,self.data_len)]]) + elif self.ins == 2: + self.put(self.start_first_sample, self.samplenum, self.out_ann, [1, [ 'ReadAddress()=0x%02X'%self.c2_data]]) + elif self.ins == 3: + self.put(self.start_first_sample, self.samplenum, self.out_ann, [1, [ 'WriteAddress(0x%02X)'%self.c2_data]]) + + self.state = 'start' + diff --git a/libsigrokdecode4DSL/decoders/rgb_led_ws281x/pd.py b/libsigrokdecode4DSL/decoders/rgb_led_ws281x/pd.py index 85bfb85a..57e4ef2e 100644 --- a/libsigrokdecode4DSL/decoders/rgb_led_ws281x/pd.py +++ b/libsigrokdecode4DSL/decoders/rgb_led_ws281x/pd.py @@ -3,7 +3,7 @@ ## ## Copyright (C) 2016 Vladimir Ermakov ## Copyright (C) 2021 Michael Miller -## Copyright (C) 2023 DreamSourceLab +## Copyright (C) 2024 DreamSourceLab ## ## This program is free software; you can redistribute it and/or modify @@ -20,6 +20,10 @@ ## along with this program; if not, see . ## +## +## 2024/7/8 DreamSourceLab : default color order update +## + import sigrokdecode as srd from functools import reduce @@ -40,9 +44,12 @@ class Decoder(srd.Decoder): {'id': 'din', 'name': 'DIN', 'desc': 'DIN data line', 'idn':'dec_rgb_led_ws281x_chan_din'}, ) options = ( - {'id': 'colors', 'desc': 'Colors', 'default': 'GRB', + {'id': 'default_color_order', 'desc': 'Default Color Order', 'default': 'GRB', 'values': ( 'GRB', 'RGB', 'BRG', 'RBG', 'BGR', 'GRBW', 'RGBW', 'WRGB', 'LBGR', 'LGRB', 'LRGB', 'LRBG', 'LGBR', 'LBRG') - , 'idn':'dec_rgb_led_ws281x_opt_colors'}, + , 'idn':'dec_rgb_led_ws281x_opt_default_color_order'}, + {'id': 'view_color_order', 'desc': 'View Color Order', 'default': 'GRB', + 'values': ( 'GRB', 'RGB', 'BRG', 'RBG', 'BGR', 'GRBW', 'RGBW', 'WRGB', 'LBGR', 'LGRB', 'LRGB', 'LRBG', 'LGBR', 'LBRG') + , 'idn':'dec_rgb_led_ws281x_opt_view_color_order'}, {'id': 'polarity', 'desc': 'Polarity', 'default': 'normal', 'values': ('normal', 'inverted'), 'idn':'dec_rgb_led_ws281x_opt_polarity'}, ) @@ -79,79 +86,60 @@ class Decoder(srd.Decoder): def handle_bits(self, samplenum): if len(self.bits) == self.colorsize: - elems = reduce(lambda a, b: (a << 1) | b, self.bits) - if self.colorsize == 24: - if self.options['colors'] == 'GRB': - rgb = (elems & 0xff0000) >> 8 | (elems & 0x00ff00) << 8 | (elems & 0x0000ff) - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['GRB#%06x' % rgb]]) - elif self.options['colors'] == 'RGB': - rgb = elems - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['RGB#%06x' % rgb]]) - elif self.options['colors'] == 'BRG': - rgb = (elems & 0xffff00) >> 8 | (elems & 0x0000ff) << 16 - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['BRG#%06x' % rgb]]) - elif self.options['colors'] == 'RBG': - rgb = (elems & 0xff0000) | (elems & 0x00ff00) >> 8 | (elems & 0x0000ff) << 8 - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['RBG#%06x' % rgb]]) - elif self.options['colors'] == 'BGR': - rgb = (elems & 0xff0000) >> 16 | (elems & 0x00ff00) | (elems & 0x0000ff) << 16 - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['BGR#%06x' % rgb]]) - else: - if self.options['colors'] == 'GRBW': - rgb = (elems & 0xff000000) >> 16 | (elems & 0x00ff0000) | (elems & 0x0000ff00) >> 8 - w = (elems & 0x000000ff) - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['GRB#%06x W#%02x' % (rgb, w)]]) - elif self.options['colors'] == 'RGBW': - rgb = (elems & 0xffffff00) >> 8 - w = (elems & 0x000000ff) - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['RGB#%06x W#%02x' % (rgb, w)]]) - elif self.options['colors'] == 'WRGB': - rgb = (elems & 0xffffff00) >> 8 - w = (elems & 0x000000ff) - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['W#%02x RGB#%06x ' % (w, rgb)]]) - elif self.options['colors'] == 'LBGR': - rgb = (elems & 0x0000ff00) | (elems & 0x00ff0000) >> 16 | (elems & 0x000000ff) << 16 - w = (elems & 0xff000000) >> 24 - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['L#%02x BGR#%06x ' % (w, rgb)]]) - elif self.options['colors'] == 'LGRB': - rgb = (elems & 0x000000ff) | (elems & 0x00ff0000) >> 8 | (elems & 0x0000ff00) << 8 - w = (elems & 0xff000000) >> 24 - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['L#%02x GRB#%06x ' % (w, rgb)]]) - elif self.options['colors'] == 'LRGB': - rgb = (elems & 0x00ffffff) - w = (elems & 0xff000000) >> 24 - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['L#%02x RGB#%06x ' % (w, rgb)]]) - elif self.options['colors'] == 'LRBG': - rgb = (elems & 0x00ff0000) | (elems & 0x0000ff00) >> 8 | (elems & 0x000000ff) << 8 - w = (elems & 0xff000000) >> 24 - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['L#%02x RBG#%06x ' % (w, rgb)]]) - elif self.options['colors'] == 'LGBR': - rgb = (elems & 0x00ff0000) >> 16 | (elems & 0x0000ffff) << 8 - w = (elems & 0xff000000) >> 24 - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['L#%02x GRB#%06x ' % (w, rgb)]]) - elif self.options['colors'] == 'LBRG': - rgb = (elems & 0x00ffff00) >> 8 | (elems & 0x000000ff) << 16 - w = (elems & 0xff000000) >> 24 - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['L#%02x BRG#%06x ' % (w, rgb)]]) - + elems = reduce(lambda a, b: (a << 1) | b, self.bits) - self.bits = [] - self.ss_packet = samplenum + default_val = 0 + view_val = 0 + + if self.colorsize == 24: + for i in range(3): + default_index = self.options['default_color_order'].find(self.options['view_color_order'][i]) + + if default_index == 0: + default_val = (elems & 0xff0000) >> 16 + elif default_index == 1: + default_val = (elems & 0x00ff00) >> 8 + elif default_index == 2: + default_val = (elems & 0x0000ff) + + if i == 0: + view_val = (default_val << 16) | view_val + elif i == 1: + view_val = (default_val << 8) | view_val + elif i == 2: + view_val = default_val | view_val + + self.put(self.ss_packet, samplenum, self.out_ann,[2, ['%s#%06x' % (self.options['view_color_order'] , view_val)]]) + + else: + for i in range(4): + default_index = self.options['default_color_order'].find(self.options['view_color_order'][i]) + + if default_index == 0: + default_val = (elems & 0xff000000) >> 24 + elif default_index == 1: + default_val = (elems & 0x00ff0000) >> 16 + elif default_index == 2: + default_val = (elems & 0x0000ff00) >> 8 + elif default_index == 3: + default_val = (elems & 0x000000ff) + + if i == 0: + view_val = (default_val << 24) | view_val + elif i == 1: + view_val = (default_val << 16) | view_val + elif i == 2: + view_val = (default_val << 8) | view_val + elif i == 3: + view_val = default_val | view_val + + self.put(self.ss_packet, samplenum, self.out_ann,[2, ['%s#%08x' % (self.options['view_color_order'] , view_val)]]) + + + + self.bits = [] + self.ss_packet = samplenum def check_bit_(self, samplenum): period = samplenum - self.ss @@ -175,8 +163,10 @@ class Decoder(srd.Decoder): def decode(self): if not self.samplerate: raise SamplerateError('Cannot decode without samplerate.') - - if len(self.options['colors']) == 4: + if len(self.options['default_color_order']) != len(self.options['view_color_order']): + raise Exception('default color order len must equal to view color order len') + + if len(self.options['default_color_order']) == 4: self.colorsize = 32 else: self.colorsize = 24 diff --git a/libsigrokdecode4DSL/decoders/smart qspi/pd.py b/libsigrokdecode4DSL/decoders/smart qspi/pd.py index 75ed0189..0668b08c 100644 --- a/libsigrokdecode4DSL/decoders/smart qspi/pd.py +++ b/libsigrokdecode4DSL/decoders/smart qspi/pd.py @@ -26,7 +26,8 @@ from enum import Enum Data = namedtuple('Data', ['ss', 'es', 'val']) ## -## 2023/4/8 DreamSourceLab : add flash module +## 2024/4/8 DreamSourceLab : add flash module +## 2024/7/5 DreamSourceLab : qpp text update ## # Key: (CPOL, CPHA). Value: SPI mode. @@ -42,20 +43,22 @@ spi_mode = { class process_enum(Enum): COMMAND = 0 WRITE_BYTE = 1 - READ_BYTE = 2 - READ_BYTE_CONTINUOUS = 3 - CONTINUOUS_READ_MODE_BITS = 4 - ADDRESS_BY_MODE = 5 - ADDRESS_24BIT = 6 - ADDRESS_32BIT = 7 - DUMMY_BY_MODE = 8 - DUMMY_8BIT = 9 - DUMMY_32BIT = 10 - DUMMY_40BIT = 11 + WRITE_BYTE_CONTINUOUS = 2 + READ_BYTE = 3 + READ_BYTE_CONTINUOUS = 4 + CONTINUOUS_READ_MODE_BITS = 5 + ADDRESS_BY_MODE = 6 + ADDRESS_24BIT = 7 + ADDRESS_32BIT = 8 + DUMMY_BY_MODE = 9 + DUMMY_8BIT = 10 + DUMMY_32BIT = 11 + DUMMY_40BIT = 12 process_text = { process_enum.COMMAND : ['Command' , 'CMD'] , process_enum.WRITE_BYTE : ['Write Data' , 'WD'] , + process_enum.WRITE_BYTE_CONTINUOUS : ['Write Data' , 'WD'] , process_enum.READ_BYTE : ['Read Data' , 'RD'] , process_enum.READ_BYTE_CONTINUOUS : ['Read Data' , 'RD'] , process_enum.ADDRESS_24BIT : ['24-Bit Address' , 'AD'] , @@ -108,6 +111,7 @@ READ_MODE_BITS_QUAD = process_info(process_enum.CONTINUOUS_READ_MODE_BITS , proc #write (io0) WRITE_BYTE_SINGLE = process_info(process_enum.WRITE_BYTE , process_mode.SINGLE) +WRITE_BYTE_QUAD_CONTINUOUS = process_info(process_enum.WRITE_BYTE_CONTINUOUS , process_mode.QUAD) #DUMMY DUMMY_CYCLE = process_info(process_enum.DUMMY_BY_MODE , process_mode.SINGLE) @@ -142,8 +146,8 @@ command = { 0x77 : ['Set Burst with Wrap' , 'SBWW' , [DUMMY_CYCLE_8BIT_QUAD , DUMMY_CYCLE_8BIT_QUAD , DUMMY_CYCLE_8BIT_QUAD , READ_BYTE_QUAD_CONTINUOUS]], 0x02 : ['Page Program' , 'PP' , [READ_ADDRESS] + [WRITE_BYTE_SINGLE] * 256], 0x12 : ['Page Program' , '4PP' , [READ_4B_ADDRESS] + [WRITE_BYTE_SINGLE] * 256], - 0x32 : ['Quad Page Program' , 'QPP' , [READ_ADDRESS] + [READ_BYTE_QUAD_CONTINUOUS]], - 0x34 : ['Quad Page Program' , '4QPP' , [READ_4B_ADDRESS] + [READ_BYTE_QUAD_CONTINUOUS]], + 0x32 : ['Quad Page Program' , 'QPP' , [READ_ADDRESS] + [WRITE_BYTE_QUAD_CONTINUOUS]], + 0x34 : ['Quad Page Program' , '4QPP' , [READ_4B_ADDRESS] + [WRITE_BYTE_QUAD_CONTINUOUS]], 0x20 : ['Sector Erase' , 'SE' , [READ_ADDRESS]], 0x21 : ['Sector Erase' , '4SE', [READ_4B_ADDRESS]], 0x52 : ['32KB Block Erase' , 'BE32' , [READ_ADDRESS]], @@ -345,14 +349,6 @@ class Decoder(srd.Decoder): else : spiMode='spi' - #self.putgse(ss,es,[7, ['%s' %spiMode.upper()]]) - #self.put(ss, es, self.out_ann, [3, ['@%02X' % self.io0data]]) - #if self.have_io1: - # self.put(ss, es, self.out_ann, [4, ['@%02X' % self.io1data]]) - #if self.have_io3: - # self.put(ss, es, self.out_ann, [5, ['@%02X' % self.io2data]]) - # self.put(ss, es, self.out_ann, [6, ['@%02X' % self.io3data]]) - if spiMode == 'qspi' or spiMode == 'dspi': qdata = [] @@ -472,11 +468,13 @@ class Decoder(srd.Decoder): elif cur_state.enum == process_enum.WRITE_BYTE or \ cur_state.enum == process_enum.READ_BYTE or \ cur_state.enum == process_enum.READ_BYTE_CONTINUOUS or \ + cur_state.enum == process_enum.WRITE_BYTE_CONTINUOUS or \ cur_state.enum == process_enum.CONTINUOUS_READ_MODE_BITS: self.puttext(origin_data[1] , origin_data[2] , cur_state.enum , origin_data[0]) - if cur_state.enum != process_enum.READ_BYTE_CONTINUOUS: + if cur_state.enum != process_enum.READ_BYTE_CONTINUOUS and \ + cur_state.enum != process_enum.WRITE_BYTE_CONTINUOUS: self.state_count += 1 if self.state_count < len(self.diagram):