From bd89d5a75139f3144874c93dede24b168875fde0 Mon Sep 17 00:00:00 2001 From: CJpower <1016753558@qq.com> Date: Mon, 26 Oct 2020 09:44:09 +0800 Subject: [PATCH 1/2] ps/2 --- libsigrokdecode4DSL/decoders/ps2/pd.py | 50 ++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 7 deletions(-) diff --git a/libsigrokdecode4DSL/decoders/ps2/pd.py b/libsigrokdecode4DSL/decoders/ps2/pd.py index 63808ec8..cf23b887 100755 --- a/libsigrokdecode4DSL/decoders/ps2/pd.py +++ b/libsigrokdecode4DSL/decoders/ps2/pd.py @@ -22,7 +22,7 @@ import sigrokdecode as srd from collections import namedtuple class Ann: - BIT, START, STOP, PARITY_OK, PARITY_ERR, DATA, WORD = range(7) + BIT, START, STOP, PARITY_OK, PARITY_ERR, DATA, WORD, ACK = range(8) Bit = namedtuple('Bit', 'val ss es') @@ -40,6 +40,12 @@ class Decoder(srd.Decoder): {'id': 'clk', 'name': 'Clock', 'desc': 'Clock line'}, {'id': 'data', 'name': 'Data', 'desc': 'Data line'}, ) + options = ( + {'id': 'HtoD_sampling_edge', 'desc': 'HtoD_sampling_edge', + 'default': 'rise', 'values': ('rise', 'fall')}, + {'id': 'DtoH_sampling_edge', 'desc': 'DtoH_sampling_edge', + 'default': 'fall', 'values': ('fall', 'rise')}, + ) annotations = ( ('bit', 'Bit'), ('start-bit', 'Start bit'), @@ -48,10 +54,11 @@ class Decoder(srd.Decoder): ('parity-err', 'Parity error bit'), ('data-bit', 'Data bit'), ('word', 'Word'), + ('ACK', 'ACK'), ) annotation_rows = ( ('bits', 'Bits', (0,)), - ('fields', 'Fields', (1, 2, 3, 4, 5, 6)), + ('fields', 'Fields', (1, 2, 3, 4, 5, 6, 7)), ) def __init__(self): @@ -61,10 +68,13 @@ class Decoder(srd.Decoder): self.bits = [] self.samplenum = 0 self.bitcount = 0 + self.state = 'NULL' + self.ss = self.es = 0 def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) - + self.HtoD = 1 if self.options['HtoD_sampling_edge'] == 'rise' else 0 + self.DtoH = 1 if self.options['DtoH_sampling_edge'] == 'fall' else 0 def putb(self, bit, ann_idx): b = self.bits[bit] self.put(b.ss, b.es, self.out_ann, [ann_idx, [str(b.val)]]) @@ -75,6 +85,7 @@ class Decoder(srd.Decoder): def handle_bits(self, datapin): # Ignore non start condition bits (useful during keyboard init). if self.bitcount == 0 and datapin == 1: + self.state = 'HtoD' return # Store individual bits and their start/end samplenumbers. @@ -115,12 +126,37 @@ class Decoder(srd.Decoder): self.putx(10, [Ann.STOP, ['Stop bit', 'Stop', 'St', 'T']]) self.bits, self.bitcount = [], 0 + self.state == 'NULL' def decode(self): while True: # Sample data bits on falling clock edge. - (clock_pin, data_pin) = self.wait({0: 'f'}) - self.handle_bits(data_pin) - if (self.bitcount == 11): - (clock_pin, data_pin) = self.wait({0: 'r'}) + if self.bitcount == 0: + (clock_pin, data_pin) = self.wait([{0: 'f',1: 'e'},{0: 'f'}]) + if (self.matched & (0b1 << 1)): + self.state = 'DtoH' + self.handle_bits(data_pin) + if (self.matched & (0b1 << 0)): + self.state = 'HtoD' + if self.state == 'HtoD': + if self.HtoD : + (clock_pin, data_pin) = self.wait({0: 'f'}) + else: + (clock_pin, data_pin) = self.wait({0: 'r'}) self.handle_bits(data_pin) + if (self.bitcount == 11): + (clock_pin, data_pin) = self.wait({0: 'r'}) + self.handle_bits(data_pin) + self.ss = self.samplenum + (clock_pin, data_pin) = self.wait({1: 'r'}) + self.es = self.samplenum + self.put(self.ss,self.es,self.out_ann,[Ann.ACK, ['ACK', 'ACK', 'ACK', 'A']]) + if self.state == 'DtoH': + if self.DtoH : + (clock_pin, data_pin) = self.wait({0: 'f'}) + else: + (clock_pin, data_pin) = self.wait({0: 'r'}) + self.handle_bits(data_pin) + if (self.bitcount == 11): + (clock_pin, data_pin) = self.wait({0: 'r'}) + self.handle_bits(data_pin) From 8f52519dbeff5e84e05ce853e6b0011ed47f0f8e Mon Sep 17 00:00:00 2001 From: CJpower <1016753558@qq.com> Date: Wed, 28 Oct 2020 10:21:24 +0800 Subject: [PATCH 2/2] ps/2 2020.10.28 --- libsigrokdecode4DSL/decoders/ps2/pd.py | 89 +++++++++++++++++--------- 1 file changed, 60 insertions(+), 29 deletions(-) diff --git a/libsigrokdecode4DSL/decoders/ps2/pd.py b/libsigrokdecode4DSL/decoders/ps2/pd.py index cf23b887..fc6972bb 100755 --- a/libsigrokdecode4DSL/decoders/ps2/pd.py +++ b/libsigrokdecode4DSL/decoders/ps2/pd.py @@ -22,7 +22,7 @@ import sigrokdecode as srd from collections import namedtuple class Ann: - BIT, START, STOP, PARITY_OK, PARITY_ERR, DATA, WORD, ACK = range(8) + BIT, HSTART, DSTART, STOP, PARITY_OK, PARITY_ERR, DATA, WORD, ACK = range(9) Bit = namedtuple('Bit', 'val ss es') @@ -37,28 +37,29 @@ class Decoder(srd.Decoder): outputs = [] tags = ['PC'] channels = ( - {'id': 'clk', 'name': 'Clock', 'desc': 'Clock line'}, - {'id': 'data', 'name': 'Data', 'desc': 'Data line'}, + {'id': 'clk', 'type': 0, 'name': 'Clock', 'desc': 'Clock line'}, + {'id': 'data', 'type': 107, 'name': 'Data', 'desc': 'Data line'}, ) options = ( - {'id': 'HtoD_sampling_edge', 'desc': 'HtoD_sampling_edge', + {'id': 'HtoD_Clock', 'desc': 'HtoD_Clock', 'default': 'rise', 'values': ('rise', 'fall')}, - {'id': 'DtoH_sampling_edge', 'desc': 'DtoH_sampling_edge', + {'id': 'DtoH_Clock', 'desc': 'DtoH_Clock', 'default': 'fall', 'values': ('fall', 'rise')}, ) annotations = ( - ('bit', 'Bit'), - ('start-bit', 'Start bit'), - ('stop-bit', 'Stop bit'), - ('parity-ok', 'Parity OK bit'), - ('parity-err', 'Parity error bit'), - ('data-bit', 'Data bit'), - ('word', 'Word'), - ('ACK', 'ACK'), + ('207', 'bit', 'Bit'), + ('109', 'HSTART', 'HSTART'), + ('50', 'DSTART', 'DSTART'), + ('1000', 'stop-bit', 'Stop bit'), + ('7', 'parity-ok', 'Parity OK bit'), + ('1000', 'parity-err', 'Parity error bit'), + ('40', 'data-bit', 'Data bit'), + ('65', 'word', 'Word'), + ('75', 'ACK', 'ACK'), ) annotation_rows = ( ('bits', 'Bits', (0,)), - ('fields', 'Fields', (1, 2, 3, 4, 5, 6, 7)), + ('fields', 'Fields', (1, 2, 3, 4, 5, 6, 7, 8)), ) def __init__(self): @@ -70,11 +71,12 @@ class Decoder(srd.Decoder): self.bitcount = 0 self.state = 'NULL' self.ss = self.es = 0 + self.HtoDss = 0 def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) - self.HtoD = 1 if self.options['HtoD_sampling_edge'] == 'rise' else 0 - self.DtoH = 1 if self.options['DtoH_sampling_edge'] == 'fall' else 0 + self.HtoD = 1 if self.options['HtoD_Clock'] == 'rise' else 0 + self.DtoH = 1 if self.options['DtoH_Clock'] == 'fall' else 0 def putb(self, bit, ann_idx): b = self.bits[bit] self.put(b.ss, b.es, self.out_ann, [ann_idx, [str(b.val)]]) @@ -86,7 +88,8 @@ class Decoder(srd.Decoder): # Ignore non start condition bits (useful during keyboard init). if self.bitcount == 0 and datapin == 1: self.state = 'HtoD' - return + (clock_pin, datapin) = self.wait({0: 'r'}) + # Store individual bits and their start/end samplenumbers. self.bits.append(Bit(datapin, self.samplenum, self.samplenum)) @@ -116,7 +119,10 @@ class Decoder(srd.Decoder): # Emit annotations. for i in range(11): self.putb(i, Ann.BIT) - self.putx(0, [Ann.START, ['Start bit', 'Start', 'S']]) + if self.state == 'HtoD': + self.putx(0, [Ann.HSTART, ['Host Start', 'HStart', 'HS']]) + if self.state == 'DtoH': + self.putx(0, [Ann.DSTART, ['Device Start', 'Device', 'DS']]) self.put(self.bits[1].ss, self.bits[8].es, self.out_ann, [Ann.WORD, ['Data: %02x' % word, 'D: %02x' % word, '%02x' % word]]) if parity_ok: @@ -132,25 +138,45 @@ class Decoder(srd.Decoder): while True: # Sample data bits on falling clock edge. if self.bitcount == 0: - (clock_pin, data_pin) = self.wait([{0: 'f',1: 'e'},{0: 'f'}]) - if (self.matched & (0b1 << 1)): - self.state = 'DtoH' - self.handle_bits(data_pin) - if (self.matched & (0b1 << 0)): + if self.HtoDss : self.state = 'HtoD' - if self.state == 'HtoD': - if self.HtoD : + (clock_pin, data_pin) = self.wait({0: 'r',1: 'l'}) + self.handle_bits(data_pin) (clock_pin, data_pin) = self.wait({0: 'f'}) else: + (clock_pin, data_pin) = self.wait([{0: 'f',1: 'r'},{0: 'f',1: 'f'},{0: 'f',1: 'h'},{0: 'f',1: 'l'}]) + if (self.matched & (0b1 << 0)): + continue + if (self.matched & (0b1 << 1)): + self.state = 'HtoD' + (clock_pin, data_pin) = self.wait({0: 'r',1: 'l'}) + self.handle_bits(data_pin) + (clock_pin, data_pin) = self.wait({0: 'f'}) + if (self.matched & (0b1 << 2)): + self.state = 'HtoD' + (clock_pin, data_pin) = self.wait({0: 'r',1: 'l'}) + self.handle_bits(data_pin) + (clock_pin, data_pin) = self.wait({0: 'f'}) + if (self.matched & (0b1 << 3)): + self.state = 'DtoH' + self.handle_bits(data_pin) + if self.state == 'HtoD': + if self.HtoD : (clock_pin, data_pin) = self.wait({0: 'r'}) + else: + (clock_pin, data_pin) = self.wait({0: 'f'}) self.handle_bits(data_pin) - if (self.bitcount == 11): + if (self.bitcount == 10): (clock_pin, data_pin) = self.wait({0: 'r'}) self.handle_bits(data_pin) + if (self.bitcount == 11): + (clock_pin, data_pin) = self.wait({0: 'f'}) + self.handle_bits(data_pin) self.ss = self.samplenum - (clock_pin, data_pin) = self.wait({1: 'r'}) + (clock_pin, data_pin) = self.wait({0: 'r'}) self.es = self.samplenum self.put(self.ss,self.es,self.out_ann,[Ann.ACK, ['ACK', 'ACK', 'ACK', 'A']]) + self.HtoDss = 0 if self.state == 'DtoH': if self.DtoH : (clock_pin, data_pin) = self.wait({0: 'f'}) @@ -158,5 +184,10 @@ class Decoder(srd.Decoder): (clock_pin, data_pin) = self.wait({0: 'r'}) self.handle_bits(data_pin) if (self.bitcount == 11): - (clock_pin, data_pin) = self.wait({0: 'r'}) - self.handle_bits(data_pin) + (clock_pin, data_pin) = self.wait([{1: 'f'},{0: 'r'}]) + if (self.matched & (0b1 << 0)): + self.handle_bits(data_pin) + self.HtoDss = 1 + if (self.matched & (0b1 << 1)): + self.handle_bits(data_pin) + self.HtoDss = 0 \ No newline at end of file